SC28L198A1BE,557 NXP Semiconductors, SC28L198A1BE,557 Datasheet - Page 19

• Manufacturer Part Number: SC28L198A1BE,557
• Description: IC UART OCTAL W/FIFO 100-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC28L198A1BE,557

• Features: False-start Bit Detection
• Number Of Channels: 8
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1210; 935262731557; SC28L198A1BE

Philips Semiconductors
Table 3. MR0– Mode Register 0
* If these bits are not 0 the characters will be stripped regardless of
bits (3:2) or (1:0)
MR0[7:6] – Control the handling of recognized Xon/Xoff or Address
characters. If set, the character codes are placed on the RxFIFO
along with their status bits just as ordinary characters are. If the
character is not pushed onto the RxFIFO, its received status will be
lost unless the receiver is operating in the block error mode, see
MR1[5] and the general discussion on receiver error handling.
Interrupt processing is not effected by the setting of these bits. See
Character recognition section.
MR0[5:4] – Controls the fill level at which a transmitter begins to
present its interrupt number to the interrupt arbitration logic. Use of
a low fill level minimizes the number of interrupts generated and
maximizes the number of transmit characters per interrupt cycle. It
also increases the probability that the transmitter will go idle for lack
of characters in the TxFIFO.
MR0[3:2] – Controls the Xon/Xoff processing logic. Auto
Transmitter flow control allows the gating of Transmitter activity by
Xon/Xoff characters received by the Channel’s receiver. Auto
Receiver flow control causes the Transmitter to emit an Xoff
Table 4. MR1 – Mode Register 1
MR1[7]: Receiver Request to Send Control
This bit controls the deactivation of the RTSN output (I/O2) by the
receiver. This output is asserted and negated by commands applied
via the command register. MR1[7] = 1 causes RTSN to be
automatically negated upon receipt of a valid start bit if the receiver
FIFO is
level falls below
members of Philips (Signets)’ UART families where the RTSN
function triggered on FIFO full. This behavior caused problems with
PC UARTs that could not stop transmission at the proper time. .
The RTSN feature can be used to prevent overrun in the receiver, by
using the RTSN output signal, to control the CTSN input of the
transmitting device.
2006 Aug 10
Bit 7
Xon/Xoff * transparency
0 – flow control characters
received are pushed onto
the
RxFIFO
1 – flow control characters
received are not pushed
onto the RxFIFO
Bit 7
RxRTS
Control
0 – off
1 – on
Octal UART for 3.3 V and 5 V supply voltage
full or greater. RTSN is reasserted when an the FIFO fill
Bit 6
ISR Read Mode
0 – ISR unmasked
1 – ISR masked
full. This constitutes a change from previous
Bit 6
Address Recognition *
transparency
0 – Address characters
received are pushed to
RxFIFO
1 – Address characters
received are not pushed
onto the RxFIFO
Bit 5
Error Mode
0 = Character
1 = Block
Bit 5:4
TxiNT
TxFIFO
interrupt
level
control
00 – empty
01 – 3/4 empty
10 – 1/2 empty
11 – not full
19
Bit 4:3
Parity Mode
00 – With Parity
01 – Force parity
10 – No parity
11 – Special Mode
ISR. If set, the ISR reads the current status masked by the IMR, i.e.
character when the RxFIFO has loaded to a depth of 12 characters.
Draining the RxFIFO to a level of 8 or less causes the Transmitter to
emit an Xon character. All transmissions require no host
involvement. A setting other than b’00 in this field precludes the use
of the command register to transmit Xon/Xoff characters.
Note: Interrupt generation in Xon/Xoff processing is controlled by the
IMR (Interrupt Mask Register) of the individual channels. The
interrupt may be cleared by a read of the XISR, the Xon/Xoff
Interrupt Status Register. Receipt of a flow control character will
always generate an interrupt if the IMR is so programmed. The
MR0[3:2] bits have effect on the automatic aspects of flow control
only, not the interrupt generation.
MR0[1:0] – This field controls the operation of the Address
recognition logic. If the device is not operating in the special or
“wake–up” mode, this hardware may be used as a general purpose
character detector by choosing any combination except b’00.
Interrupt generation is controlled by the channel IMR. The interrupt
may be cleared by a read of the XISR, the Xon/Xoff Interrupt Status
Register. See further description in the section on the Wake Up
mode.
MR1[6]: Interrupt Status Masking
This bit controls the readout mode of the Interrupt Status Register,
only interrupt sources enabled in the IMR can ever show a ’1’ in the
ISR. If cleared, the ISR shows the current status of the interrupt
source without regard to the Interrupt Mask setting.
MR1[5]: Error Mode Select
This bit selects the operating mode of the three FIFOed status bits
(FE, PE, received break). In the character mode, status is provided
on a character by character basis; the status applies only to the
character at. the bottom of the FIFO. In the block mode, the status
provided in the SR for these bits is the accumulation (logical OR) of
Bit 3:2
In–band flow control mode
00 – host mode, only the host CPU
may initiate flow control actions
through the CR
01 – Auto Transmitter flow control
10 – Auto Receiver flow control
11 – Auto Receiver and Transmitter
flow control
Bit 2
Parity Type
0 = Even
1 = Odd
Bit 1:0
Address Recognition
control
00 – none
01 – Auto wake
10 – Auto doze
11 – Auto wake and
auto doze
SC28L198
Bit 1:0
Bits per Charac-
ter
00 – 5
01 – 6
10 – 7
11 – 8
Product data sheet