SC16C654BIA68,512 NXP Semiconductors, SC16C654BIA68,512 Datasheet - Page 34

• Manufacturer Part Number: SC16C654BIA68,512
• Description: ID QUAD UART 64BYTE 68PLCC
• Manufacturer: NXP Semiconductors

Specifications of SC16C654BIA68,512

• Features: False-start Bit Detection
• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Transmit Fifo: 64Byte
• Receive Fifo: 64Byte
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935274935512; SC16C654BIA68; SC16C654BIA68

Philips Semiconductors
9397 750 14965
Product data sheet
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the modem, or
other peripheral device to which the SC16C654B/654DB is connected. Four bits of this
register are used to indicate the changed information. These bits are set to a logic 1
whenever a control input from the modem changes state. These bits are set to a logic 0
whenever the CPU reads this register.
Table 21:
[1]
Bit
7
6
5
4
3
2
1
0
Whenever any MSR bit 0:3 is set to logic 1, a Modem Status Interrupt will be generated.
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
MSR[1]
MSR[0]
Modem Status Register bits description
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Description
CD (active HIGH, logical 1). Normally this bit is the complement of the CD
input. In the loop-back mode this bit is equivalent to the OP2 bit in the MCR
register.
RI (active HIGH, logical 1). Normally this bit is the complement of the RI input.
In the loop-back mode this bit is equivalent to the OP1 bit in the MCR register.
DSR (active HIGH, logical 1). Normally this bit is the complement of the DSR
input. In loop-back mode this bit is equivalent to the DTR bit in the MCR
register.
CTS. CTS functions as hardware flow control signal input if it is enabled via
EFR[7]. The transmit holding register flow control is enabled/disabled by
MSR[4]. Flow control (when enabled) allows starting and stopping the
transmissions based on the external modem CTS signal. A logic 1 at the CTS
pin will stop SC16C654B/654DB transmissions as soon as current character
has finished transmission. Normally MSR[4] is the complement of the CTS
input. However, in the loop-back mode, this bit is equivalent to the RTS bit in
the MCR register.
CD
RI
DSR
CTS
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C654B/654DB has changed state since
the last time it was read. A modem Status Interrupt will be generated.
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C654B/654DB has changed from a logic 0
to a logic 1. A modem Status Interrupt will be generated.
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C654B/654DB has changed state since
the last time it was read. A Modem Status Interrupt will be generated.
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C654B/654DB has changed state since
the last time it was read. A Modem Status Interrupt will be generated.
[1]
Rev. 02 — 20 June 2005
[1]
[1]
[1]
SC16C654B/654DB
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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