SC16C754BIBM,151 NXP Semiconductors, SC16C754BIBM,151 Datasheet - Page 21

• Manufacturer Part Number: SC16C754BIBM,151
• Description: IC UART QUAD W/FIFO 64-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C754BIBM,151

• Number Of Channels: 4, QUART
• Package / Case: 64-LQFP
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3290; 935279069151; SC16C754BIBM-S

NXP Semiconductors
7. Register descriptions
SC16C754B_4
Product data sheet
Each register is selected using address lines A0, A1, A2, and in some cases, bits from
other registers. The programming combinations for register selection are shown in
Table
Table 9.
[1]
[2]
[3]
[4]
[5]
[6]
A2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
Fig 14. Crystal oscillator connection
MCR[7] can only be modified when EFR[4] is set.
Accessed by a combination of address pins and register bits.
Accessible only when LCR[7] is logic 1.
Accessible only when LCR is set to 1011 1111 (BFh).
Accessible only when EFR[4] = 1 and MCR[6] = 1, that is, EFR[4] and MCR[6] are read/write enables.
Accessible only when CSA to CSD = 0, MCR[2] = 1, and loopback is disabled (MCR[4] = 0).
A1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
1
1
1
9.
Register map - read/write properties
A0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
Read mode
Receive Holding Register (RHR)
Interrupt Enable Register (IER)
Interrupt Identification Register (IIR)
Line Control Register (LCR)
Modem Control Register (MCR)
Line Status Register (LSR)
Modem Status Register (MSR)
ScratchPad Register (SPR)
Divisor Latch LSB (DLL)
Divisor Latch MSB (DLM)
Enhanced Feature Register (EFR)
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmission Control Register
(TCR)
Trigger Level Register (TLR)
FIFO ready register
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
[2][5]
Rev. 04 — 6 October 2008
XTAL1
1.8432 MHz
[2][4]
[2][4]
[2][4]
[2][4]
C1
22 pF
X1
XTAL2
[2][6]
C2
33 pF
[2][3]
[2][3]
[2][5]
[1]
[2][4]
XTAL1
1.8432 MHz
Write mode
Transmit Holding Register (THR)
Interrupt Enable Register (IER)
FIFO Control Register (FCR)
Line Control Register (LCR)
Modem Control Register (MCR)
not applicable
not applicable
ScratchPad Register (SPR)
Divisor Latch LSB (DLL)
Divisor Latch MSB (DLM)
Enhanced Feature Register (EFR)
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmission Control Register
(TCR)
Trigger Level Register (TLR)
C1
22 pF
X1
[2][5]
XTAL2
002aaa870
[2][4]
[2][4]
[2][4]
[2][4]
1.5 k
C2
47 pF
SC16C754B
© NXP B.V. 2008. All rights reserved.
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