PEF 82912 F V1.4 Infineon Technologies, PEF 82912 F V1.4 Datasheet - Page 69

• Manufacturer Part Number: PEF 82912 F V1.4
• Description: IC MODULAR ISDN NT INTELL TQFP64
• Manufacturer: Infineon Technologies
• Series: Q-SMINT®r

Specifications of PEF 82912 F V1.4

• Function: Second Generation Modular
• Interface: ISDN
• Mounting Type: Surface Mount
• Package / Case: 64-LFTQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -
• Power (watts): -
• Operating Temperature: -
• Number Of Circuits: -
• Other names: PEF82912FV1.4XT; PEF82912FV14XP; SP000007558; SP000007559

•
Figure 29
2.3.5.4
In intelligent NT applications (selected via register S_MODE.MODE2-0) the Q-SMINT I
has to share the upstream D-channel with one or more D-channel controllers on the
IOM -2 interface and with all connected TEs on the S interface.
The S-transceiver incorporates an elaborate state machine for D-channel priority
handling on IOM -2
arbitration mechanism as on the S interface (writing D-bits, reading back E-bits) is
performed for all D-channel sources on IOM -2. Due to this an equal and fair access is
guaranteed for all D-channel sources on both the S interface and the IOM -2 interface.
The access to the upstream D-channel is handled via the S/G bit for the HDLC
controllers and via E-bit for all connected terminals on S (E-bits are inverted to block the
terminals on S). Furthermore, if more than one HDLC source is requesting D-channel
access on IOM -2 the TIC bus mechanism is used (see
The arbiter permanently counts the “1s” in the upstream D-channel on IOM -2. If the
necessary number of “1s” is counted and an HDLC controller on IOM -2 requests
upstream D-channel access (BAC bit is set to 0), the arbiter allows this D-channel
controller immediate access and blocks other TEs on S (E-bits are inverted). Similar as
on the S-interface the priority for D-channel access on IOM -2 can be configured to 8 or
10 (S_CMD.DPRIO).
The configuration settings of the Q-SMINT I in intelligent NT applications are
summarized in
Data Sheet
DD
D-Channel Arbitration
B1
Structure of Last Octet of Ch2 on DD
Table
B2
12.
(Chapter
MON
0
D CI0
2.3.5.5). For the access to the D-channel a similar
MR
MX
IC1
Stop/Go
IC2
55
S/G A/B
MON1
CI1
Available/Blocked
Chapter
MR
MX
Functional Description
2.3.5.2).
PEF 82912/82913
S/G
ITD09693.vsd
2001-03-30
A/B