TP11362AN National Semiconductor, TP11362AN Datasheet - Page 9

• Manufacturer Part Number: TP11362AN
• Description: IC PROCESSOR QUAD DIFF PCM 24DIP
• Manufacturer: National Semiconductor

Specifications of TP11362AN

• Function: Adaptive Differential Pulse Code Modulation (ADPCM) Transcoder
• Interface: PCM, Serial
• Number Of Circuits: 4
• Voltage - Supply: 5V
• Current - Supply: 7mA
• Power (watts): 35mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *TP11362AN

Functional Description
G.726. At power up, the outputs TSO and RSO are in
TRI-STATE mode. This “cold” reset process is asynchronous
and takes approximately 2000 CLK cycles for the initializa-
tion. During the reset process, the outputs TSO and RSO are
in TRI-STATE mode.
CHANNEL NOP
Each channel can be independently disabled. When EN is at
logic low on the falling edge of CE, the ADPCM transcoder
processing for that channel is disabled. The processor re-
quires 4 CLK cycles for CE to maintain all channel variables.
The data output ports are also placed in known states. After
this the processor waits for the next interrupt. Power is con-
served during this time by disabling the internal registers.
TSO outputs the following data after a channel NOP:
QSEL1
0
0
1
1
TABLE 6. TSO at Channel NOP
QSEL0
0
1
0
1
32 kbps
24 kbps
16 kbps
40 kbps
Mode
(Continued)
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0 0
TSO
9
The data pattern at TSO in Table 6 are shown with 3 ASCK
rising edges within the CE high pulse for the 32, 24, 16 kbps
modes and 4 ASCK rising edges within the CE high pulse for
the 40 kbps mode (the MSB is shifted out with the falling
edge of CE). In the idle case (NOP) where EN is low at the
falling edge of CE, the TSO output is low for the duration of
the high CE pulse.
In the idle state (NOP), RSO outputs the following data (bit
representation with the sign-bit on the left followed by the
MSB, the sign-bit is the first bit after the rising edge of CE):
PCM1
0
1
TABLE 7. RSO at Channel NOP
8-Bit A-Law
8-Bit µ-Law
Mode
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
RSO
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