DS2155G+T&R Maxim Integrated Products, DS2155G+T&R Datasheet - Page 212
![IC TXRX T1/E1/J1 1 CHIP 100CSBGA](/photos/6/94/69414/100-csbga_21-0153b_sml.jpg)
DS2155G+T&R
Manufacturer Part Number
DS2155G+T&R
Description
IC TXRX T1/E1/J1 1 CHIP 100CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2155L.pdf
(238 pages)
Specifications of DS2155G+T&R
Function
Single-Chip Transceiver
Interface
E1, HDLC, J1, T1
Number Of Circuits
1
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LFBGA
Includes
BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
- Current page: 212 of 238
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Figure 35-9. Transmit-Side 1.544MHz Boundary Timing (Elastic Store
Enabled)
Note 1: TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG is ignored during channel 24).
Figure 35-10. Transmit-Side 2.048MHz Boundary Timing (Elastic Store
Enabled)
Note 1: TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored.
Note 2: TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored).
Note 3: TCHBLK is forced to 1 in the same channels as TSER is ignored (see Note 1).
Note 4: The F-bit position for the T1 frame is sampled and passed through the transmit-side elastic store into the MSB bit position of channel 1.
TCHBLK
(Normally, the transmit-side formatter overwrites the F-bit position unless the formatter is programmed to pass through the F-bit
position.)
TSYSCLK
TSYSCLK
TCHBLK
TCHCLK
TSSYNC
TCHCLK
TSSYNC
TSER
TSER
TSIG
TSIG
2,3
1
1
CHANNEL 23
CHANNEL 31
CHANNEL 31
CHANNEL 23
A
A
B
B
C/A D/B
C/A D/B
LSB MSB
LSB MSB
212 of 238
CHANNEL 24
CHANNEL 24
CHANNEL 32
CHANNEL 32
A
A
B
B
C/A D/B
C/A D/B
LSB
LSB
F
F MSB
4
CHANNEL 1
CHANNEL 1
CHANNEL 1
CHANNEL 1
A
A
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