DS2155G+T&R Maxim Integrated Products, DS2155G+T&R Datasheet - Page 109

IC TXRX T1/E1/J1 1 CHIP 100CSBGA

DS2155G+T&R

Manufacturer Part Number
DS2155G+T&R
Description
IC TXRX T1/E1/J1 1 CHIP 100CSBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS2155G+T&R

Function
Single-Chip Transceiver
Interface
E1, HDLC, J1, T1
Number Of Circuits
1
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LFBGA
Includes
BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
20.
The DS2155 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode
is enabled, the data stream presented at TSER already has the FAS/NFAS, CRC multiframe alignment
word, and CRC-4 checksum in time slot 0. The user can modify the Sa bit positions. This change in data
content is used to modify the CRC-4 checksum. This modification, however, does not corrupt any error
information the original CRC-4 checksum may contain. In this mode of operation, TSYNC must be
configured to multiframe mode. The data at TSER must be aligned to the TSYNC signal. If TSYNC is an
input, then the user must assert TSYNC aligned at the beginning of the multiframe relative to TSER. If
TSYNC is an output, the user must multiframe-align the data presented to TSER.
Figure 20-1. CRC-4 Recalculate Method
G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)
TPOSO/TNEGO
INSERT
NEW CRC-4
CODE
EXTRACT
OLD CRC-4
CODE
+
CRC-4
CALCULATOR
109 of 238
XOR
NEW Sa BIT
DATA
MODIFY
Sa BIT
POSITIONS
TSER

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