DS2153Q-A7+T&R Maxim Integrated Products, DS2153Q-A7+T&R Datasheet - Page 23

IC TXRX E1 1-CHIP 5V 44-PLCC

DS2153Q-A7+T&R

Manufacturer Part Number
DS2153Q-A7+T&R
Description
IC TXRX E1 1-CHIP 5V 44-PLCC
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS2153Q-A7+T&R

Function
Single-Chip Transceiver
Interface
E1
Number Of Circuits
1
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
65mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
SR2: STATUS REGISTER 2 (Address = 07 Hex)
(MSB)
RMF
SYMBOL
RCMF
LOTC
TSLIP
RMF
TMF
RAF
TAF
SEC
RAF
POSITION
SR2.7
SR2.6
SR2.5
SR2.4
SR2.3
SR2.2
SR2.1
SR2.0
TMF
NAME AND DESCRIPTION
Receive CAS Multiframe. Set every 2ms (regardless if CAS
signaling is enabled or not) on receive multiframe boundaries. Used
to alert the host that signaling data is available.
Receive Align Frame. Set every 250ms at the beginning of align
frames. Used to alert the host that Si and Sa bits are available in the
RAF and RNAF registers.
Transmit Multiframe. Set every 2µs (regardless if CRC4 is
enabled) on transmit multiframe boundaries. Used to alert the host
that signaling data needs to be updated.
1-Second Timer. Set on increments of 1 second based on RCLK. If
CCR2.7 = 1, then this bit will be set every 62.5ms instead of once a
second.
Transmit Align Frame. Set every 250µs at the beginning of align
frames. Used to alert the host that the TAF and TNAF registers
need to be updated.
Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for one channel time (or 3.9µs). Will force pin 16 high
if enabled via TCR2.0. Based on RCLK.
Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries;
will continue to be set every 2ms on an arbitrary boundary if CRC4
is disabled.
Transmit Elastic Store Slip. Set when the elastic store has either
repeated or deleted a frame of data.
SEC
23 of 60
TAF
LOTC
RCMF
TSLIP
(LSB)

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