SI3019-F-GSR Silicon Laboratories Inc, SI3019-F-GSR Datasheet - Page 63

• Manufacturer Part Number: SI3019-F-GSR
• Description: IC VOICE DAA GCI/PCM/SPI 16SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3019-F-GSR

• Function: Data Access Arrangement (DAA)
• Interface: GCI, PCM, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Includes: Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant

Register 4. Interrupt Source
Reset settings = 0000_0000
Bit
7
6
5
4
3
2
Name
Type
Bit
LCSOI
Name
ROVI
DODI
RDTI
BTDI
FDTI
RDTI
R/W
D7
Ring Detect Interrupt.
0 = A ring signal is not occurring.
1 = A ring signal is detected. If the RDTM bit (Register 3) and INTE bit (Register 2) are set, a
hardware interrupt occurs on the AOUT/INT pin. This bit must be written to a 0 to be cleared.
The RDI bit (Register 2) determines if this bit is set only at the beginning of a ring pulse, or at
the both the beginning and end of a ring pulse. This bit should be cleared after clearing the
PDL bit (Register 6) as powering up the line-side device can cause this interrupt to be trig-
gered.
Receive Overload Interrupt.
0 = Normal operation.
1 = An excessive input level on the receive pin is detected. If the ROVM bit (Register 3) and
INTE bit (Register 2) are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must
be written to 0 to clear it. This bit is identical in function to the ROV bit (Register 17) and clear-
ing this bit also clears the ROV bit.
Frame Detect Interrupt.
0 = Frame detect is established on the ISOcap link.
1 = This bit is set when the ISOcap link does not have frame lock. If the FDTM bit (Register 3)
and INTE bit (Register 2) are set, a hardware interrupt occurs on the AOUT/INT pin. When
set, this bit must be written to 0 to be cleared.
Billing Tone Detect Interrupt.
0 = Normal operation.
1 = The line-side power supply has been disrupted. If the BTDM bit (Register 3) and INTE bit
(Register 2) are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be writ-
ten to 0 to clear it.
Drop Out Detect Interrupt.
0 = Normal operation.
1 = The line-side power supply has collapsed. (The DOD bit in Register 19 has fired.) If the
DODM bit (Register 3) and INTE bit (Register 2) are set, a hardware interrupt occurs on the
AOUT/INT pin. This bit must be written to 0 to be cleared. This bit should be cleared after
clearing the PDL bit (Register 6) as powering up the line-side device can cause this interrupt
to be triggered.
Loop Current Sense Overload Interrupt.
0 = Normal operation.
1 = The LCS bits have reached max value. If the LCSOM bit (Register 3) and the INTE bit are
set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to clear it.
Note: LCSOI does not necessarily imply that an overcurrent situation has occurred. An overcurrent
situation in the DAA is determined by the status of the OPD bit (Register 19). After the LCSOI
interrupt fires, the OPD bit should be checked to determine if an overcurrent situation exists.
ROVI
R/W
D6
FDTI
R/W
D5
Rev. 1.31
BTDI
R/W
D4
Function
DODI
R/W
D3
Si3050 + Si3018/19
LCSOI
R/W
D2
TGDI
R/W
D1
POLI
R/W
D0
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