SI3019-F-FM Silicon Laboratories Inc, SI3019-F-FM Datasheet
SI3019-F-FM
Specifications of SI3019-F-FM
Related parts for SI3019-F-FM
SI3019-F-FM Summary of contents
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Features PCM highway data interface µ-law/A-law companding SPI control interface GCI interface dynamic range TX/RX Line voltage monitor ...
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Si3050 + Si3011/18/19 2 Rev. 1.4 ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si3050 + Si3011/18/19 5.37. Companding in GCI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical Specifications Table 1. Recommended Operating Conditions and Thermal Information 1 Parameter Ambient Temperature Si3050 Supply Voltage, Digital Thermal Resistance (Si3011/18/19) 3 Thermal Resistance (Si3050) Notes: 1. The Si3050 specifications are guaranteed when the typical application circuit (including component ...
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Si3050 + Si3011/18/19 Table 2. Loop Characteristics = = (V 3 °C, see Figure 1 on page Parameter Symbol DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination ...
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Table 3. DC Characteristics 3 ° Parameter 1 High Level Input Voltage 1 Low Level Input Voltage High Level Output Voltage Low Level Output Voltage AOUT ...
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Si3050 + Si3011/18/19 Table 4. AC Characteristics = = Fs = 8000 Hz, (V 3 ° Parameter Sample Rate PCLK Input Frequency Receive Frequency Response Receive Frequency Response 1 Transmit Full-Scale ...
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Table 4. AC Characteristics (Continued 8000 Hz, (V 3 ° Parameter 8 Dynamic Range (Caller ID mode) 8 Caller ID Full-Scale Level 6,9 Gain Accuracy 10 Transhybrid ...
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Si3050 + Si3011/18/19 Table 6. Switching Characteristics—General Inputs = = = (V 3 ° Parameter Cycle Time, PCLK PCLK Duty Cycle PCLK Jitter Tolerance Rise Time, PCLK Fall ...
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Table 7. Switching Characteristics—Serial Peripheral Interface = = = (V 3 ° Parameter* Cycle Time SCLK Rise Time, SCLK Fall Time, SCLK Delay Time, SCLK Fall to SDO Active ...
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Si3050 + Si3011/18/19 Table 8. Switching Characteristics—PCM Highway Serial Interface = = = (V 3 ° Parameter Cycle Time PCLK Valid PCLK Inputs 2 FSYNC Period PCLK Duty ...
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Table 9. Switching Characteristics—GCI Highway Serial Interface = = = (V 3 ° Parameter Cycle Time PCLK (Single Clocking Mode) Cycle Time PCLK (Double Clocking Mode) Valid PCLK ...
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Si3050 + Si3011/18/19 PCLK FSYNC DRX DTX Figure 6. GCI Highway Interface Timing Diagram (2x PCLK Mode) Table 10. Digital FIR Filter Characteristics—Transmit and Receive = = (V 3.0 to 3.6 V, Sample Rate 8 kHz Parameter Passband ...
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Figure 7. FIR Receive Filter Response Figure 8. FIR Receive Filter Passband Ripple For Figures 7–10, all filter plots apply to a sample rate kHz. For Figures 11–14, all filter plots apply to a sample rate ...
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Si3050 + Si3011/18/19 Figure 11. IIR Receive Filter Response Figure 12. IIR Receive Filter Passband Ripple Figure 13. IIR Transmit Filter Response 16 Figure 14. IIR Transmit Filter Passband Ripple Figure 15. IIR Receive Group Delay Figure 16. IIR Transmit ...
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Typical Application Schematic Si3050 + Si3011/18/19 Rev. 1.4 17 ...
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Si3050 + Si3011/18/19 IGND EPAD EPAD EPAD 47K NI R53 47K NI R52 18 Rev. 1.4 ...
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Bill of Materials Component C1 C5, C6, C50, C51 C7 C8, C9 C10 1 C30, C31 2 D1, D2 Dual Diode, 225 mA, 300 V, (CMPD2004S) FB1, FB2, FB203, FB204 Q1 Q4, Q5 ...
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Si3050 + Si3011/18/19 4. AOUT PWM Output Figure 19 illustrates an optional circuit to support the pulse width modulation (PWM) output capability of the Si3050 for call progress monitoring purposes.To enable this mode, the INTE bit (Register 2) should be ...
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... Three different line-side devices are available for use with the Si3050 system-side device. The Si3011 line-side device has been optimized for TBR21 and FCC-compliant countries. The Si3018 and Si3019 line-side devices are globally compliant, have a selectable 200 Hz RX high-pass filter pole, and offer a – ...
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Si3050 + Si3011/18/19 Table 13. Country-specific Register Settings Register 16 Country OHS Argentina 0 1 Australia 1 Austria 0 Bahrain 0 Belgium 0 Brazil 0 Bulgaria 0 Canada 0 Chile 0 China 0 Colombia 0 Croatia 0 Cyprus 0 Czech ...
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Table 13. Country-specific Register Settings (Continued) Register 16 31 Country OHS OHS2 Ireland 0 Israel 0 Italy 0 Japan 0 Jordan 0 Kazakhstan 0 Kuwait 0 Latvia 0 Lebanon 0 Luxembourg 0 Macao 0 2 Malaysia 0 Malta 0 Mexico ...
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Si3050 + Si3011/18/19 Table 13. Country-specific Register Settings (Continued) Register 16 Country OHS Slovakia 0 Slovenia 0 South Africa 0 South Korea 0 Spain 0 Sweden 0 Switzerland 0 Taiwan 0 3 TBR21 0 Thailand 0 UAE 0 United Kingdom ...
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Power Supplies The Si3050 operates from a 3.3 V power supply. The Si3050 input pins require 3.3 V CMOS signal levels. If support signal levels is necessary, a level shifter is required. The Si3011/18/19 derives its ...
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Si3050 + Si3011/18/19 5.6. Calibration The Si3050 initiates two auto-calibrations by default when the device goes off-hook or experiences a loss of line power resistor calibration is performed to allow circuitry internal to the DAA to adjust ...
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... DODM bit is set) indicating that the line-derived power supply has collapsed. With the Si3019 line side, the LVS bits also can be read when on- or off-hook to determine the line voltage. Significant drops in line voltage can signal a parallel handset ...
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... Si3050 + Si3011/18/19 5.12.1. Line Voltage Measurement (Si3011 and Si3019 Line Side Devices Only) The Si3050 reports line voltage with the LVS[7:0] bits (Register 29) in both on- and off-hook states with a resolution per bit. The accuracy of these bits is approximately ±10%. Bits 0 through 7 of this 8-bit signed number indicate the value of the line voltage in 2s complement format ...
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Loop Current Measurement When the Si3050 is off-hook, the LCS[4:0] bits measure loop current in 3.3 mA/bit resolution. With the LCS[4:0] bits, a user can detect another phone going off-hook by monitoring the dc loop current. The line current ...
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... Register 3 and bit 1 in Register 44 can be set to enable Venkel, SMEC, hardware interrupt sources (bit 0 is available with the Panasonic Si3011 and Si3019 line-side devices only). When one or more of these bits is set, the AOUT/INT pin goes into an Panasonic active state and stays active until the interrupts are serviced ...
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CVT[7:0] bits. Therefore, only positive numbers should be used as a threshold. 5.16. DC Termination The DAA has programmable settings for the dc impedance, current limiting, minimum operational loop current and TIP/RING voltage. The dc impedance of the DAA is ...
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... The Si3019 provides sixteen impedances when used with the Si3050. The ACIM[3:0] bits in Register 30 are used to select the ac impedance setting on the Si3019. The sixteen available settings for the Si3019 are listed in Table 18. The most widely used ac terminations are available as register options to ...
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Ring Detection The ring signal is resistively coupled from TIP and RING to the RNG1 and RNG2 pins. The Si3050 supports either full- or half-wave ring detection. With full-wave ring detection, the designer can detect a polarity reversal of ...
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Si3050 + Si3011/18/19 5.19. Ring Validation Ring validation prevents false triggering of a ring detection by validating the ring parameters. Invalid signals, such as a line-voltage change when a parallel handset goes off-hook, pulse dialing high-voltage line test ...
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... ROVM and INTE bits. Certain events such as billing tones can be sufficiently large to disrupt the line-derived power supply of the Voice DAA line side device (Si3011, Si3018 or Si3019.) To ensure that the device maintains the off-hook line state during these events, the BTE bit should be set. If such an event occurs while the BTE bit is set, the BTD and BTDI bits will be asserted ...
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... RNG 1/2 pins and presented to the host via the DTX pin. 4. Clear the ONHM bit after the caller ID data is received. 5.25.2. Type II Caller ID (Si3011 and Si3019 Line-Side Device Only) Type II Caller ID sends the CID data while the phone is off-hook. This mode is often referred to as caller ID/ call waiting (CID/CW) ...
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Set the OH bit to return to an off-hook state. Immediately after returning to an off-hook state, the off-hook counter must be allowed to expire. This allows the line voltage to settle before transmitting or receiving data. After 8 ...
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Si3050 + Si3011/18/19 5.27. Gain Control The Si3050 supports multiple levels of gain and attenuation for the transmit and receive paths. The TXG2 and RXG2 bits (Registers 38–39) enable gain or attenuation increments for the transmit and ...
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Filter Selection The Si3050 supports additional filter selections for the receive and transmit signals as defined in Tables 10 and 11. The IIRE bit (Register 16, bit 4) selects between the IIR and FIR filters. The IIR filter provides ...
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Si3050 + Si3011/18/19 Table 20. PCM or GCI Highway Mode Selection SCLK Note: Values shown are the states of the pins at the rising edge of RESET. Table 21. Pin Functionality in PCM or GCI Highway Mode ...
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By setting the correct starting point of the data, the Si3050 can operate with buses having multiple devices requiring different time slots. The DTX pin is high impedance except during transmission of an 8-bit PCM sample. DTX returns to high ...
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Si3050 + Si3011/18/ I Figure 31. PCM ...
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PCLK FSYNC PCLK_CNT DRX M SB DTX HI Figure 33. PCM Highway Double Clocked Transmission, Short FSYNC (TXS = RXS = 0, PHCF = 1, TRI = 1) Si3050 + Si3011/18/ ...
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Si3050 + Si3011/18/19 5.33. Companding in PCM Mode The Si3050 supports both µ-Law and A-Law companding formats in addition to 16-bit linear data. The 8-bit companding schemes follow a segmented curve formatted as a sign bit, three chord bits, and ...
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Table 22. µ-Law Encode-Decode Characteristics Segment #Intervals x Interval Size Number 256 128 ...
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Si3050 + Si3011/18/19 Table 23. A-Law Encode-Decode Characteristics Segment #Intervals x interval size Number 128 ...
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SPI Control Interface The control interface to the Si3050 is a 4-wire interface modeled on commonly available micro-controller and serial peripheral devices. The interface consists of four pins: clock (SCLK), chip select (CS), serial data input (SDI), and serial ...
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Si3050 + Si3011/18/19 SDO SCLK CPU CS SDI Figure 36. SPI Daisy Chain Control Architecture BRCT R SDI0 SDI1 SDI2 SDI3 ...
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SDI0-15 Figure 38. Sample SPI Control Byte for Broadcast Mode (Write Only) In Figure 37 the CID field this field is decremented in LSB to MSB order, the value decrements for each SDI down the line. ...
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Si3050 + Si3011/18/ CLK S DI CONTROL S DO Figure 42. Read Operation via a 16-bit SPI Port Figures 41 and 42 illustrate WRITE and READ operations via a 16-bit SPI controller. These operations require a 4-byte ...
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Within the SC channel are six Command/Indicate (C/I) bits and two handshaking bits (MR and MX). The C/I bits are used for status and command communication, whereas the handshaking ...
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Si3050 + Si3011/18/19 1st Byte MX Transm itter MX MR Receiver MR 1st Byte Figure 44. Monitor Handshake Timing The Idle state is achieved by the MX and MR bits being held inactive (signal is high) for two or more ...
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In this manner, multiple consecutive registers can be read or written in one transmission sequence. By correctly manipulating the MX and MR bits, a transmission sequence can continue from the beginning specified address until an invalid memory location is reached. ...
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Si3050 + Si3011/18/19 The data presented to the Si3050 in the downstream Monitor bits must be present for two consecutive frames to be considered valid data. The Si3050 checks to ensure it receives the same data in two consecutive frames. ...
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MR x MXR MR x MXR Wait Idle RQT MR x RQT 1s t Byte EOM RQT nth Byte MR ack ...
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Si3050 + Si3011/18/19 56 Rev. 1.4 ...
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Si3050 + Si3011/18/19 Rev. 1.4 57 ...
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Si3050 + Si3011/18/19 5.40. Summary of Monitor Channel Commands Communication with the Si3050 should be in the following format: Byte 1: Device Address Byte Byte 2: Command Byte Byte 3: Register Address Byte Bytes 4-n: Data Bytes Bytes n+1, n+2: ...
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Response to CID command from the device using channel B2 is placed in Monitor Data. When bits A and B are channel enable bits. When these bits are set to 1, the individual corresponding ...
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Si3050 + Si3011/18/19 CIR1: OH Data that is received must be consistent and match for at least two consecutive frames to be considered valid. When a new command or status is communicated via the C/I bits, the data must be ...
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Transmit SC Channel The following diagram shows the definition of the transmitted SC channel, which is transmitted MSB first. MSB CIT6 CIT5 CIT4 These bits are defined as follows: CIT6: Reserved CIT5: CVI CIT4: DOD CIT3: ...
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... Programmable Hybrid Register 1–8 53–58 Reserved 59 Spark Quenching Control Notes: 1. Bit is available for Si3019 line-side device only. 2. Bit is available for Si3011 and Si3019 line-side devices only. 3. Bit is available for Si3018 and Si3019 line-side devices only. 62 Table 25. Register Summary Bit 7 Bit 6 Bit 5 Bit 4 SR ...
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Register 1. Control 1 Bit Name R/W Type Reset settings = 0000_0000 Bit Name 7 SR Software Reset Enables the DAA for normal operation Sets all registers to their reset value. Note: Bit ...
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Si3050 + Si3011/18/19 Register 2. Control 2 Bit D7 D6 INTE INTP Name R/W R/W Type Reset settings = 0000_0011 Bit Name 7 INTE Interrupt Pin Enable The AOUT/INT pin functions as an analog output for call progress ...
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... The TGD bit going active causes an interrupt on the AOUT/INT pin. 0 POLM Polarity Reversal Detect Mask (Si3011 and Si3019 line-side only). This interrupt is generated from bit 7 of the LVS register. When this bit transitions, it indicates that the polarity of TIP and RING is switched. ...
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Si3050 + Si3011/18/19 Register 4. Interrupt Source Bit D7 D6 RDTI ROVI Name R/W R/W Type Reset settings = 0000_0000 Bit Name 7 RDTI Ring Detect Interrupt ring signal is not occurring ring signal ...
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... AOUT/INT pin. To clear the interrupt, write this bit POLI Polarity Reversal Detect Interrupt (Si3011 and Si3019 line-side only Bit 7 of the LVS register has not changed states Bit 7 of the LVS register has transitioned from from indicating the polarity of TIP and RING is switched ...
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Si3050 + Si3011/18/19 Register 5. DAA Control 1 Bit D7 D6 RDTN Name R Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 RDTN Ring Detect Signal Negative negative ring signal is occurring. ...
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Register 6. DAA Control 2 Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4 PDL Powerdown Line-Side Device Normal operation. Program the clock generator before clearing this bit ...
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Si3050 + Si3011/18/19 Register 8-9. Reserved Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 Reserved Read returns zero. Register 10. DAA Control 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved ...
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... LSID[3:0] Line-Side ID Bits. These four bits will always read one of the following values, depending on which line-side device is used: Device Si3011 Si3018 Si3019 3:0 REVA[3:0] System-Side Revision. Four-bit value indicating the revision of the Si3050 (system-side) device. Register 12. Line-Side Device Status Bit D7 D6 ...
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Si3050 + Si3011/18/19 Register 13. Line-Side Device Revision Bit Name R Type Reset settings = xxxx_xxxx Bit Name 7 Reserved Read returns zero. 6 Reserved This bit always reads a one. 5:2 REVB[3:0] Line-Side Device Revision. Four-bit ...
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Register 15. TX/RX Gain Control 1 Bit D7 D6 TXM Name R/W Type Reset settings = 0000_0000 Bit Name 7 TXM Transmit Mute Transmit signal is not muted Mutes the transmit signal. 6:4 Reserved Read returns ...
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... For Si3011 line-side device, this bit may be written to a zero or one Ringer Threshold Select. Si3018 and Si3019 line-side only. This bit, in combination with the RT2 bit, is used to satisfy country requirements on ring detec- tion. Signals below the lower level do not generate a ring detection; signals above the upper level are guaranteed to generate a ring detection ...
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... Disable auto-calibration. 4 RT2 Ringer Threshold Select 2. Si3018 and Si3019 line-side only. This bit, in combination with the RT bit, is used to satisfy country requirements on ring detec- tion. Signals below the lower level do not generate a ring detection; signals above the upper level are guaranteed to generate a ring detection. ...
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Si3050 + Si3011/18/19 Bit Name 1 ROV Receive Overload. This bit is set when the receive input has an excessive input level (i.e., receive pin goes below ground). Writing this location clears this bit and the ROVI ...
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Register 19. International Control 4 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 OVL Receive Overload Detect. This bit has the same function as ROV (Register 17), but clears itself after ...
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Si3050 + Si3011/18/19 Register 20. Call Progress RX Attenuation Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 ARM[7:0] AOUT Receive Path Attenuation. When decremented from the default setting, these bits linearly attenuate the AOUT receive path ...
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Register 22. Ring Validation Control 1 Bit D7 D6 RDLY[1:0] Name R/W Type Reset settings = 1001_0110 Bit Name Ring Delay Bits 1 and 0. 7:6 RDLY[1:0] These bits, in combination with the RDLY[2] bit (Register 23), set the amount ...
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Si3050 + Si3011/18/19 Register 23. Ring Validation Control 2 Bit D7 D6 RDLY[2] Name R/W Type Reset settings = 0010_1101 Bit Name 7 RDLY[2] Ring Delay Bit 2. This bit, in combination with the RDLY[1:0] bits (Register 22), sets the ...
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Register 24. Ring Validation Control 3 Bit D7 D6 RNGV Name R/W Type Reset settings = 0001_1001 Bit Name 7 RNGV Ring Validation Enable Ring validation feature is disabled Ring validation feature is enabled in both ...
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... For Si3011 line-side device, these bits may be written to a zero or one. 5:4 MINI[1:0] Minimum Operational Loop Current. Si3018 and Si3019 line-side only. Adjusts the minimum loop current at which the DAA can operate. Increasing the minimum operational loop current can improve signal headroom at a lower TIP/RING voltage. ...
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Register 27. Reserved Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not write to these register bits. Register 28. Loop Current Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 ...
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Si3050 + Si3011/18/19 Register 30. AC Termination Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 Reserved This bit may be written to a zero or one. Enhanced Full Scale (2x) ...
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... Bit Name 7 FULL Full Scale Transmit and Receive Mode. Si3018 and Si3019 line-side only Default Transmit/receive full scale. This bit changes the full scale of the ADC and DAC from 0 dBm min to +3.2 dBm into a 600 load (or 1 dBV into all reference impedances). When this bit is set, the DCV[1:0] bits (Register 26) should be set to all 1s ...
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Si3050 + Si3011/18/19 Register 32. Ground Start Control Bit D7 D6 Name Type Reset settings = 0000_0x11 Bit Name 7:3 Reserved Read returns zero. 2 TGD TIP Ground Detect The CO has grounded TIP, causing current to flow. ...
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Register 33. PCM/SPI Mode Select Bit D7 D6 PCML Name R/W R/W Type Reset settings = 0000_0000 Bit Name 7 PCML PCM Analog Loopback Normal operation Enables analog data to be received from the line, converted ...
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Si3050 + Si3011/18/19 Register 34. PCM Transmit Start Count—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 TXS[7:0] PCM Transmit Start Count. PCM Transmit Start Count equals the number of PCLKs following FSYNC before data ...
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Register 37. PCM Receive Start Count—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 RXS[1:0] PCM Receive Start Count. PCM Receive Start Count equals the number of PCLKs following FSYNC ...
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Si3050 + Si3011/18/19 Register 39. RX Gain Control 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA2 Receive Gain or Attenuation Incrementing the RXG2[3:0] bits results in ...
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Register 40. TX Gain Control 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 TGA3 Transmit Gain or Attenuation Incrementing the TGA3[3:0] bits results in gaining up the ...
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Si3050 + Si3011/18/19 Register 41. RX Gain Control 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA3 Receive Gain or Attenuation Incrementing the RXG3[3:0] bits results in ...
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Register 42. GCI Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3:2 GCIF[1:0] GCI Data Format A-Law µ-Law 8-bit linear. The top 8-bits of the ...
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... These bits determine the threshold at which an interrupt is generated from either the LCS or LVS register. This interrupt can be generated to occur when the line current or line voltage rises above or drops below the value in the CVT[7:0] register. Register 44. Line Current/Voltage Threshold Interrupt Control (Si3011 and Si3019 line-side only) Bit D7 ...
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Register 45. Programmable Hybrid Register 1 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB1[7:0] Programmable Hybrid Register 1. These bits can be programmed with a coefficient value to adjust the hybrid response to reduce near-end ...
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Si3050 + Si3011/18/19 Register 47. Programmable Hybrid Register 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB3[7:0] Programmable Hybrid Register 3. These bits can be programmed with a coefficient value to adjust the hybrid response ...
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Register 49. Programmable Hybrid Register 5 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB5[7:0] Programmable Hybrid Register 5. These bits can be programmed with a coefficient value to adjust the hybrid response to reduce near-end ...
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Si3050 + Si3011/18/19 Register 51. Programmable Hybrid Register 7 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB7[7:0] Programmable Hybrid Register 7. These bits can be programmed with a coefficient value to adjust the hybrid response ...
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... Reserved Always write this bit to zero. 4 SQ0 Spark Quenching. Si3018 and Si3019 line-side only. This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets the amount of time for the line-side device to go on-hook. The on-hook speeds specified are measured from the time the OH bit is cleared until loop current equals zero ...
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Si3050 + Si3011/18/19 FSYNC PCKLK DRX RGDT AOUT/INT 100 CS GND 1 18 VDD Si3050 Top View DTX C1A 4 15 C2A 5 14 GND RESET 6 13 Figure 50. Si3050 QFN SDITHRU SDO 1 ...
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Table 26. Si3050 Pin Descriptions QFN TSSOP Pin Name Pin # Pin # 23 1 SDO Serial Port Data Output. Serial port control data output SDI Serial Port Data Input. Serial port control data input ...
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Si3050 + Si3011/18/19 Table 26. Si3050 Pin Descriptions (Continued) QFN TSSOP Pin Name Pin # Pin # 14 14 C2A Isolation Capacitor 2A. Connects to one side of the isolation capacitor C2. Used to communicate with the line-side device. 15 ...
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Pin Descriptions: Si3011/18/19 Figure 53. Si3011/18/19 SOIC/TSSOP Si3050 + Si3011/18/ DCT3 IGND PAD C1B 4 13 QE2 C2B ...
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Si3050 + Si3011/18/19 SOIC/ QFN TSSOP Pin Name Pin # Pin # connect Transistor Emitter. Connects to the emitter of Q3 DCT DC Termination. Provides dc termination to the telephone network. 2 ...
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Table 27. Si3011/18/19 Pin Descriptions (Continued) SOIC/ QFN TSSOP Pin Name Pin # Pin # 17 15 IGND Isolated Ground. Connects to ground on the line-side interface DCT2 DC Termination 2. Provides dc termination to the telephone network. ...
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... Si3019-F-GS Line-side Voice DAA-Enhanced Global Si3019-F-FT Line-side Voice DAA-Enhanced Global Si3019-F-GT Line-side Voice DAA-Enhanced Global Si3019-F-FM Line-side Voice DAA-Enhanced Global Si3019-F-GM Line-side Voice DAA-Enhanced Global Notes: 1. Adding the suffix “R” to the end of the part number (e.g., Si3050-E-FTR) denotes tape-and-reel packaging. ...
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Product Identification The product identification number is a finished goods part number or is specified by a finished goods part number, such as a special customer part number. Example: Si3050-E-FSR Product Designator Product Revision Si3050 + Si3011/18/19 Shipping Option ...
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Si3050 + Si3011/18/19 10. Package Outline: 20-Pin TSSOP Figure 54 illustrates the package details for the Si3050. Table 28 lists the values for the dimensions shown in the illustration. Figure 54. 20-Pin Thin Shrink Small Outline Package (TSSOP) 108 Rev. ...
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Table 28. 20-Pin TSSOP Package Diagram Dimensions Dimension θ aaa bbb ccc Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing ...
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Si3050 + Si3011/18/19 10.1. PCB Land Pattern: Si3050 TSSOP Figure 55. 20-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Pattern Table 29. 20-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Pattern Dimensions Dimension ...
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Package Outline: 24-Pin QFN Figure 56 illustrates the package details for the Si3050. Table 30 lists the values for the dimensions shown in the illustration. Si3050 + Si3011/18/19 Figure 56. 24-Pin QFN Package Rev. 1.4 111 ...
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Si3050 + Si3011/18/19 Table 30. 24-Pin QFN Package Dimensions Dimension aaa bbb ccc ddd eee 112 MIN NOM 0.80 — 0.00 — 0.18 — 4.00 BSC 2.05 2.20 0.50 BSC 4.00 ...
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PCB Land Pattern: Si3050 QFN Figure 57. 24-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Si3050 + Si3011/18/19 Rev. 1.4 113 ...
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Si3050 + Si3011/18/19 Table 31. 24-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Dimensions Symbol Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is ...
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Package Outline: 16-Pin SOIC Figure 58 illustrates the package details for the Si3011/18/19. Table 32 lists the values for the dimensions shown in the illustration. Figure 58. 16-Pin Small Outline Integrated Circuit (SOIC) Package Si3050 + Si3011/18/19 Rev. 1.4 ...
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Si3050 + Si3011/18/19 Table 32. 16-Pin SOIC Package Diagram Dimensions Dimension θ aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
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PCB Land Pattern: Si3011/18/19 SOIC Figure 59. 16-Pin Small Outline Integrated Circuit (SOIC) PCB Land Pattern Table 33. 16-Pin Small Outline Integrated Circuit (SOIC) PCB Land Pattern Dimensions Dimension Notes: 1. This Land Pattern ...
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Si3050 + Si3011/18/19 14. Package Outline: 16-Pin TSSOP Figure 60 illustrates the package details for the Si3011/18/19. Table 34 lists the values for the dimensions shown in the illustration. Figure 60. 16-Pin Thin Shrink Small Outline Package (TSSOP) 118 Rev. ...
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Table 34. 16-Pin TSSOP Package Diagram Dimensions Dimension Min A — A1 0.05 A2 0.80 b 0.19 c 0. 0.45 L2 θ 0° aaa bbb ccc Notes: 1. All dimensions shown are in ...
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Si3050 + Si3011/18/19 14.1. PCB Land Pattern: Si3011/18/19 TSSOP Figure 61. 16-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Pattern Table 35. 16-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Patten Dimensions Dimension ...
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Package Outline: 20-Pin QFN Figure 62 illustrates the package details for the Si3011/18/19. Table 36 lists the values for the dimensions shown in the illustration. Figure 62. 20-Pin Quad Flat No-Lead (QFN) Package Si3050 + Si3011/18/19 Rev. 1.4 ...
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Si3050 + Si3011/18/19 Table 36. 20-Pin QFN Package Diagram Dimensions Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
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PCB Land Pattern: Si3011/18/19 QFN Figure 63. 20-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Si3050 + Si3011/18/19 Rev. 1.4 123 ...
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Si3050 + Si3011/18/19 Table 37. 20-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Dimensions Dimension 124 MIN MAX 2.71 REF 1.60 1.80 0.50 BSC 2.71 REF 1.60 1.80 2.53 ...
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Table 37. 20-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Dimensions (Continued) Dimension ZE ZD Notes: General 1. All dimensions shown are in milllimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This ...
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Si3050 + Si3011/18/ Si3050 S ILICON ABS AN30: Ground Start Implementation with Silicon Laboratories’ DAAs AN67: Layout Guidelines AN72: Ring Detection/Validation with the Si305x DAAs AN84: Digital Hybrid with the Si305x DAAs Si3050PPT-EVB Data ...
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... Revision 1.1 to Revision 1.31 The internal System-Side Revision value (REVA[3:0] in Register 11) has been incremented by one for Si3050 revision E. Revision 1.31 to Revision 1.4 Added Si3011 device specifications Added Si3050, Si3011, Si3018, and Si3019 QFN information Rev. 1.4 127 ...
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