DS2151QB+ Maxim Integrated Products, DS2151QB+ Datasheet - Page 42

• Manufacturer Part Number: DS2151QB+
• Description: IC TXRX T1 1-CHIP 5V LP 44-PLCC
• Manufacturer: Maxim Integrated Products

Specifications of DS2151QB+

• Function: Single-Chip Transceiver
• Interface: T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 65mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC, 44-PLCC
• Includes: Alarm Detector and Generator, CSU Loop Codes Generator and Detector, DSX-1 and CSU Line Build-Outs Generator
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

13.3 Jitter Attenuator
The DS2151Q contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via
the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications
where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications.
The characteristics of the attenuation are shown in
either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.
Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA-bit in the LICR. In order
for the jitter attenuator to operate properly, a crystal with the specifications listed in
must be connected to the XTAL1 and XTAL2 pins. The jitter attenuator divides the clock provided by the
6.176MHz crystal at the XTAL1 and XTAL2 pins to create an output clock that contains very little jitter.
On-board circuitry will pull the crystal (by switching in or out load capacitance) to keep it long-term
averaged to the same frequency as the incoming T1 signal. If the incoming jitter exceeds either 120UI
(buffer depth is 128 bits) or 28UI
crystal by either 3.5 or 4.5 instead of the normal 4 to keep the buffer from overflowing. When the device
divides by either 3.5 or 4.5, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive
Information Register 2 (RIR2.2).
Table 13-4. Crystal Selection Guidelines
Parallel Resonant Frequency
Mode
Load Capacitance
Tolerance
Pullability
Effective Series Resistance
Crystal Cut
PARAMETER
6.176MHz
Fundamental
18pF to 20pF (18.5pF nominal)
±50ppm
C
+250ppm
C
40Ω maximum
AT
P-P
L
L
(buffer depth is 32 bits), then the DS2151Q will divide the attached
= 10pF, delta frequency = +175ppm to
= 45pF, delta frequency = -175ppm to -250ppm
42 of 60
SPECIFICATION
Figure
13-4. The jitter attenuator can be placed in
Table 13-4
below
P-P