P87LPC760BDH NXP Semiconductors, P87LPC760BDH Datasheet - Page 31
P87LPC760BDH
Manufacturer Part Number
P87LPC760BDH
Description
MCU 8-Bit 87LP 80C51 CISC 1KB EPROM 5V 14-Pin TSSOP Tube
Manufacturer
NXP Semiconductors
Datasheet
1.P87LPC760BN112.pdf
(56 pages)
Specifications of P87LPC760BDH
Package
14TSSOP
Device Core
80C51
Family Name
87LP
Maximum Speed
20 MHz
Ram Size
128 Byte
Program Memory Size
1 KB
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Program Memory Type
EPROM
Number Of Programmable I/os
12
Interface Type
I2C/UART
Operating Temperature
0 to 70 °C
Number Of Timers
2
Philips Semiconductors
Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer,
which is an 8-bit Counter with a divide-by-32 prescaler. Figures 24
and 25 show Mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As
the count rolls over from all 1s to all 0s, it sets the Timer interrupt
flag TFn. The count input is enabled to Timer 0 when TR0 = 1 and
either GATE = 0 or INT0 = 1. (Setting GATE = 1 allows the Timer to
be controlled by external input INT0, to facilitate pulse width
2002 Mar 07
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
TCON
OSC/6
OSC/12
BIT
TCON.7
TCON.6
TCON.5
TCON.4
TCON.3, 2
TCON.1
TCON.0
INT0 PIN
T0 PIN
GATE
TR0
Address: 88h
Bit Addressable
OR
SYMBOL
TF1
TR1
TF0
TR0
IE0
IT0
–
TF1
7
FUNCTION
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
interrupt is processed, or by software.
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off.
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
processor vectors to the interrupt routine, or by software.
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.
Reserved (must be 0).
Interrupt 0 Edge flag. Set by hardware when external interrupt 0 edge is detected. Cleared by
hardware when the interrupt is processed, or by software.
Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupts.
Figure 24. Timer/Counter 0 in Mode 0 (13-Bit Timer/Counter)
C/T = 1
C/T = 0
TR1
Figure 23. Timer/Counter Control Register (TCON)
6
TF0
5
CONTROL
TR0
4
28
3
–
measurements). TRn is a control bit in the Special Function Register
TCON (Figure 23). The GATE bit is in the TMOD register (TMOD.3).
The 13-bit register consists of all 8 bits of THn and the lower 5 bits
of TLn. The upper 3 bits of TLn are indeterminate and should be
ignored. Setting the run flag (TRn) does not clear the registers.
Mode 0 operation is slightly different for Timer 0 and Timer 1. See
Figures 24 and 25.
(5 BITS)
TL0
2
–
(8 BITS)
IE0
TH0
1
TOGGLE
OVERFLOW
IT0
0
T0OE
TF0
P87LPC760
Reset Value: 00h
SU01543
INTERRUPT
Preliminary data
T0 PIN
SU01544