P87LPC760BDH NXP Semiconductors, P87LPC760BDH Datasheet - Page 17

• Manufacturer Part Number: P87LPC760BDH
• Description: MCU 8-Bit 87LP 80C51 CISC 1KB EPROM 5V 14-Pin TSSOP Tube
• Manufacturer: NXP Semiconductors

Specifications of P87LPC760BDH

• Package: 14TSSOP
• Device Core: 80C51
• Family Name: 87LP
• Maximum Speed: 20 MHz
• Ram Size: 128 Byte
• Program Memory Size: 1 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 12
• Interface Type: I2C/UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 2

Philips Semiconductors
Regarding Software Response Time
Because the P87LPC760 can run at 20 MHz, and because the I
interface is optimized for high-speed operation, it is quite likely that
an I
at a rising edge of SCL) and write I2DAT before SCL has gone low
again. If XDAT were applied directly to SDA, this situation would
produce an I
about this possibility because XDAT is applied to SDA only when
SCL is low.
Conversely, a program that includes an I
a long time to respond to DRDY. Typically, an I
on a flag-polling basis during a message, with interrupts from other
peripheral functions enabled. If an interrupt occurs, it will delay the
response of the I
about this very much either, because the I
SCL low time until the service routine responds. The only constraint
on the response is that it must not exceed the Timer I time-out.
Values to be used in the CT1 and CT0 bits are shown in Table 2. To
allow the I
oscillator frequency, compare the actual oscillator rate to the f OSC
2002 Mar 07
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
I2CFG
2
C service routine will sometimes respond to DRDY (which is set
BIT
I2CFG.7
I2CFG.6
I2CFG.5
I2CFG.4
I2CFG.2, 3
I2CFG.1, 0 CT1, CT0
2
C bus to run at the maximum rate for a particular
2
C protocol violation. The programmer need not worry
Address: C8h
Bit Addressable
2
C service routine. The programmer need not worry
SYMBOL
MASTRQ
SLAVEN
TIRUN
CLRTI
—
SLAVEN
7
FUNCTION
Slave Enable. Writing a 1 this bit enables the slave functions of the I
MASTRQ are 0, the I
time-out.
Master Request. Writing a 1 to this bit requests mastership of the I
progress when this bit is changed from 0 to 1, action is delayed until a stop condition is detected. A
start condition is sent and DRDY is set (thus making ATN = 1 and generating an I
When a master wishes to release mastership status of the I
MASTRQ is cleared by an I
Writing a 1 to this bit clears the Timer I overflow flag. This bit position always reads as a 0.
Writing a 1 to this bit lets Timer I run; a zero stops and clears it. Together with SLAVEN, MASTRQ,
and MASTER, this bit determines operational modes as shown in Table 1.
Reserved for future use. Should not be set to 1 by user programs.
These two bits are programmed as a function of the CPU clock rate, to optimize the MIN HI and LO
time of SCL when this device is a master on the I
controls both of these parameters, and also the timing for stop and start conditions.
MASTRQ
2
C service routine may take
2
C hardware stretches the
6
2
C routine operates
Figure 8. I
CLRTI
5
2
C hardware is disabled. This bit is cleared to 0 by reset and by an I
2
C Configuration Register (I2CFG)
TIRUN
2
2
C
C time-out.
4
14
—
3
max column in the table. The value for CT1 and CT0 is found in the
first line of the table where CPU clock max is greater than or equal
to the actual frequency.
Table 2 also shows the machine cycle count for various settings of
CT1/CT0. This allows calculation of the actual minimum high and
low times for SCL as follows:
For instance, at an 8 MHz frequency, with CT1/CT0 set to 1 0, the
minimum SCL high and low times will be 5.25 s.
Table 2 also shows the Timer I timeout period (given in machine
cycles) for each CT1/CT0 combination. The timeout period varies
because of the way in which minimum SCL high and low times are
measured. When the I
at every SCL transition with a value dependent upon CT1/CT0. The
pre-load value is chosen such that a minimum SCL high or low time
has elapsed when Timer I reaches a count of 008 (the actual value
pre-loaded into Timer I is 8 minus the machine cycle count).
SCL min high/low time in microseconds = 6 * Min Time Count
—
2
2
C. The time value determined by these bits
CT1
1
2
C, it writes a 1 to XSTP in I2CON.
2
C interface is operating, Timer I is pre-loaded
2
C bus. If a transmission is in
2
CT0
C subsystem. If SLAVEN and
0
Reset Value: 00h
2
C interrupt).
P87LPC760
CPU clock in MHz
2
C
Preliminary data
SU01552