ISP1161A1BD,118 NXP Semiconductors, ISP1161A1BD,118 Datasheet - Page 88
ISP1161A1BD,118
Manufacturer Part Number
ISP1161A1BD,118
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1161A1BD118.pdf
(137 pages)
Specifications of ISP1161A1BD,118
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
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Philips Semiconductors
9397 750 13961
Product data
12.3 DACK-only mode
The following example shows the steps which occur in a typical DMA transfer:
10. The 8237 de-asserts the DACK output indicating that the ISP1161A1’s DC must
11. The 8237 places the bus control signals (MEMR, MEMW, IOR and IOW) and the
12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating
For a typical bulk transfer the above process is repeated, once for each byte. After
each byte the address register in the DMA controller is incremented and the byte
counter is decremented. When using 16-bit DMA the number of transfers is 32, and
address incrementing and byte counter decrementing is done by 2 for each word.
The DACK-only DMA mode is selected by setting bit DAKOLY in the
DcHardwareConfiguration register (see
shown in
mode is given in
1. The ISP1161A1’s DC receives a data packet in one of its endpoint FIFOs; the
2. The ISP1161A1’s DC asserts the DREQ2 signal requesting the 8237 for a DMA
3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.
4. After completing the current instruction cycle, the CPU places the bus control
5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR
6. The 8237 asserts DACK to inform the ISP1161A1’s DC that it will start a DMA
7. The ISP1161A1’s DC now places the word to be transferred on the data bus
8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This
9. The ISP1161A1’s DC de-asserts the DREQ2 signal to indicate to the 8237 that
packet must be transferred to memory address 1234H.
transfer.
signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and
asserts HLDA to inform the 8237 that it has control of the bus.
control signals.
transfer.
lines, because its RD signal was asserted by the 8237.
latches and stores the word at the desired memory location. It also informs the
ISP1161A1’s DC that the data on the bus lines has been transferred.
DMA is no longer needed. In Single cycle mode this is done after each word, in
Burst mode following the last transferred word of the DMA cycle.
stop placing data on the bus.
address lines in three-state and de-asserts the HRQ signal, informing the CPU
that it has released the bus.
the bus control lines (MEMR, MEMW, IOR and IOW) and the address lines, the
CPU resumes the execution of instructions.
Table
72. A typical example of the ISP1161A1’s DC in DACK-only DMA
Rev. 03 — 23 December 2004
Figure
41.
USB single-chip host and device controller
Table
82). The pin functions for this mode are
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1161A1
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