MT48LC2M32B2TG-7:GTR Micron Technology Inc, MT48LC2M32B2TG-7:GTR Datasheet - Page 56
![](/photos/40/77/407734/tsop-ii-86_sml.jpg)
MT48LC2M32B2TG-7:GTR
Manufacturer Part Number
MT48LC2M32B2TG-7:GTR
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2TG-7GTR.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-7:GTR
Organization
2Mx32
Density
64Mb
Address Bus
13b
Access Time (max)
17/8/5.5ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
160mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Figure 38:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Single READ
DQML, DQMH
COMMAND
BA0, BA1
Notes:
DQM /
A0-A9
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
1. For this example, BL = 1, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A8, A9 = “Don’t Care.”
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
T1
NOP
DISABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
T2
BANK
READ
t CH
t CMH
CAS Latency
56
SINGLE BANK
PRECHARGE
ALL BANKS
BANK
T3
t LZ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t RP
t AC
T4
NOP
D
OUT
t OH
t HZ
m
BANK
ROW
T5
ROW
ACTIVE
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
DON’T CARE
UNDEFINED
Timing Diagrams