MT48LC2M32B2TG-7:GTR Micron Technology Inc, MT48LC2M32B2TG-7:GTR Datasheet - Page 38
![](/photos/40/77/407734/tsop-ii-86_sml.jpg)
MT48LC2M32B2TG-7:GTR
Manufacturer Part Number
MT48LC2M32B2TG-7:GTR
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2TG-7GTR.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-7:GTR
Organization
2Mx32
Density
64Mb
Address Bus
13b
Access Time (max)
17/8/5.5ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
160mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Figure 30:
Table 8:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
CKE
H
H
L
L
n - 1
Internal
States
Truth Table 2 – CKE
Notes: 1–4 apply to entire table
WRITE with Auto Precharge Interrupted by a WRITE
CKE
H
H
L
L
Notes:
n
COMMAND
ADDRESS
Note:
BANK m
BANK n
CLK
DQ
1. CKE
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
Reading or writing
Current State
Clock suspend
Clock suspend
clock edge.
COMMAND
clock edge n + 1 (provided that
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the
period.
the next command at clock edge n + 1.
All banks idle
All banks idle
Power-down
Power-down
DQM is LOW.
Self refresh
Self refresh
Page Active
T0
n
NOP
is the logic state of CKE at clock edge n; CKE
t
WRITE - AP
n
n
XSR period. A minimum of two NOP commands must be provided during
BANK n,
Page Active
BANK n
.
COL a
T1
D
is the command registered at clock edge n, and ACTION
a
IN
WRITE with Burst of 4
a + 1
T2
D
NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
IN
See Table 9 on page 39
38
AUTO REFRESH
WRITE or NOP
COMMAND
a + 2
T3
D
t
NOP
CKS is met).
IN
X
X
X
X
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK m,
WRITE - AP
COL d
BANK m
T4
D
d
t
n
IN
WR - BANK n
Interrupt Burst, Write-Back
WRITE with Burst of 4
T5
n - 1
d + 1
NOP
D
IN
was the state of CKE at the previous
Maintain clock suspend
Maintain power-down
Maintain self refresh
Clock suspend entry
Power-down entry
Exit clock suspend
Exit power-down
Self refresh entry
T6
Exit self refresh
d + 2
NOP
D
t RP - BANK n
IN
Precharge
ACTION
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
DON’T CARE
n
T7
d + 3
NOP
D
t WR - BANK m
n
is a result of
IN
Write-Back
Commands
Notes
t
7
XSR is
5
6
t
XSR