MT47H64M16HR-3:HTR Micron Technology Inc, MT47H64M16HR-3:HTR Datasheet - Page 122
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MT47H64M16HR-3:HTR
Manufacturer Part Number
MT47H64M16HR-3:HTR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT47H64M16HR-3HTR.pdf
(136 pages)
Specifications of MT47H64M16HR-3:HTR
Lead Free Status / Rohs Status
Compliant
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Table 44: Truth Table – CKE
Notes 1–4 apply to the entire table
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. W 7/11 EN
Current State
Bank(s) active
All banks idle
Power-down
Self refresh
Previous Cycle
Notes:
(n - 1)
H
H
H
H
L
L
L
L
10. Valid commands for self refresh exit are NOP and DESELECT only.
11. Power-down and self refresh can not be entered while READ or WRITE operations,
12. Minimum CKE high time is
13. Self refresh mode can only be entered from the all banks idle state.
14. Must be a legal command, as defined in Table 37 (page 73).
1. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.
3. Command (n) is the command registered at clock edge n, and action (n) is a result of
4. The state of ODT does not affect the states described in this table. The ODT function is
5. Power-down modes do not perform any REFRESH operations. The duration of power-
6. “X” means “Don’t Care” (including floating around V
7. All states and sequences not shown are illegal or reserved unless explicitly described
8. Valid commands for power-down entry and exit are NOP and DESELECT only.
9. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge oc-
previous clock edge.
command (n).
not available during self refresh (see ODT Timing (page 130) for more details and spe-
cific restrictions).
down mode is therefore limited by the refresh requirements.
down. However, ODT must be driven high or low in power-down if the ODT function is
enabled via EMR.
elsewhere in this document.
curring during the
clocks) is satisfied.
LOAD MODE operations, or PRECHARGE operations are in progress. See SELF REFRESH
(page 118) and SELF REFRESH (page 79) for a list of detailed restrictions.
This requires a minimum of 3 clock cycles of registration.
CKE
Cycle (n)
Current
H
H
H
L
L
L
L
L
t
XSNR period. READ commands may be issued only after
CS#, RAS#, CAS#,
122
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
Command (n)
t
CKE = 3 ×
Refresh
WE#
Shown in Table 37 (page 73)
X
X
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
CK. Minimum CKE LOW time is
1Gb: x4, x8, x16 DDR2 SDRAM
Active power-down en-
Precharge power-down
Maintain power-down
Maintain self refresh
Self refresh entry
Power-down exit
Self refresh exit
Action (n)
REF
entry
) in self refresh and power-
try
Power-Down Mode
2007 Micron Technology, Inc. All rights reserved.
t
CKE = 3 ×
7, 8, 11, 12
10, 12, 13
t
7, 9, 10
7, 8, 11
XSRD (200
Notes
5, 6
7, 8
14
6
t
CK.
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