MT47H64M16HR-3:HTR Micron Technology Inc, MT47H64M16HR-3:HTR Datasheet - Page 118
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT47H64M16HR-3:HTR
Manufacturer Part Number
MT47H64M16HR-3:HTR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT47H64M16HR-3HTR.pdf
(136 pages)
Specifications of MT47H64M16HR-3:HTR
Lead Free Status / Rohs Status
Compliant
- Current page: 118 of 136
- Download datasheet (3Mb)
SELF REFRESH
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. W 7/11 EN
The SELF REFRESH command is initiated when CKE is LOW. The differential clock
should remain stable and meet
fresh mode. The procedure for exiting self refresh requires a sequence of commands.
First, the differential clock must be stable and meet
prior to CKE going back to HIGH. Once CKE is HIGH (
with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com-
mands issued for
ments is used to apply NOP or DESELECT commands for 200 clock cycles before apply-
ing any other command.
t
XSNR. A simple algorithm for meeting both refresh and DLL require-
118
t
CKE specifications at least 1 ×
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
t
CK specifications at least 1 ×
t
CKE [MIN] has been satisfied
2007 Micron Technology, Inc. All rights reserved.
t
CK after entering self re-
SELF REFRESH
t
CK
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