STA2064N STMicroelectronics, STA2064N Datasheet - Page 8

• Manufacturer Part Number: STA2064N
• Description: IC APPL PROCESSOR 289TFBGA
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STA2064N

• Applications: GPS
• Core Processor: ARM11
• Program Memory Type: -
• Controller Series: Cartesio™
• Ram Size: 8K x 32
• Interface: AC97, CAN, I²C, MSP, MMC/SD, SPDIF, SSP, UART, USB
• Number Of I /o: 65
• Voltage - Supply: 1.8 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11636

System description
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
8/19
Communication interfaces
USB
STA2064 embeds one USB2.0 OTG high-speed interface, featuring:
To reduce total system cost, it is equipped with a built-in USB 2.0 PHY.
With the goal of reducing the BOM cost for the customer, the USB 2.0 PHY also supports
this additional muxing scheme:
●
●
UART
STA2064 features four Autobaud UARTs. One offers all modem control/status signals. They
are enhanced version of the industry-standard 16C550 UART.
I
The I
according to I
that provides a low-cost interconnection between ICs. STA2064 features three I
interfaces.
MSP
The multichannel serial port (MSP) is a synchronous receive and transmit serial interface.
STA2064 features three MSPs.
SSP
STA2064 features two SSPs up to 24Mbit/sec for synchronous serial communication with
external peripherals. SPI, MicroWire, T.I. and mono-directional protocols are supported with
programmable word length up to 32 bits.
SPDIF
This interface takes SPDIF as input and extracts data and other channel information
encrypted in SPDIF Frame format as per IEC958 standards. Data can be transferred to
memory, using DMA support, or directly to C3 decoder without CPU intervent. SPDIF block
supports up to 2X data streams.
2
C
a)
b)
c)
d)
e)
f)
the USB D- wire is used as either the USB D- signal or UART receive data signal
the USB D+ wire is used as either the USB D+ signal or the UART transmit data signal
2
C controller is an interface designed to support the physical and data link layer
High-speed signalling rate at 480 Mbit/s
Support for full-speed (12 Mbit/s) signaling bit rate
Support for session request protocol (SRP) and host negotiation protocol (HNP)
Up to 7 bidirectional endpoints plus control endpoint 0
8192 bytes maximum FIFO dimension
Dynamic FIFO allocation
2
C standard revision 2.1 (January 2000). The I
Doc ID 16057 Rev 3
2
C bus is a 2-wire serial bus
2
C
STA2064