STA2064N STMicroelectronics, STA2064N Datasheet - Page 5

• Manufacturer Part Number: STA2064N
• Description: IC APPL PROCESSOR 289TFBGA
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STA2064N

• Applications: GPS
• Core Processor: ARM11
• Program Memory Type: -
• Controller Series: Cartesio™
• Ram Size: 8K x 32
• Interface: AC97, CAN, I²C, MSP, MMC/SD, SPDIF, SSP, UART, USB
• Number Of I /o: 65
• Voltage - Supply: 1.8 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11636

STA2064
2
2.1
2.2
2.2.1
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
System description
MCU
ARM1176-JZF advanced risc machine CPU up to 533 MHz (with Vdd greater or equal to
1.20 V and under process and temperature worst case conditions).
Embedded memories
Embedded SRAM (eSRAM)
The embedded SRAM is 8K x 32 (32 KB).
System functions
System and reset controller (SRC)
This provides a control interface for clock generation components external to the subsystem.
It also controls system-wide and peripherals-specific energy management features.
PMU
The power manager module controls the SLEEP to DEEP-SLEEP modes transition,
controls the external voltage switches on the Vdd and Vddio, monitors the external power
supply (via two signals, Vddok and BATOK), can force the emergency entry of the SDRAM
in self-refresh, and controls the wake-up from DEEP-SLEEP mode.
DMA
Direct memory access can be used with DMA peripherals. FIFO fill/empty requests from
these peripherals can be serviced immediately by the DMA Controller without CPU
interaction. Peripheral-to-peripheral and memory-to-memory DMA are also supported.
STA2064 features two DMA engines. Each DMA supports up to 8-channels and up to 32
requests.
Vectored interrupt controller (VIC)
The VIC allows the OS interrupt handler to quickly dispatch interrupt service routines in
response to peripheral interrupts.
GPIOs
Four GPIO ports provide 65 programmable inputs or outputs that can be controlled in two
modes:
●
●
software mode through an APB bus interface
hardware mode through a hardware control interface
Doc ID 16057 Rev 3
System description
5/19