STM32F407IGT6 STMicroelectronics, STM32F407IGT6 Datasheet - Page 48

IC MCU 32BIT 1MB FLASH 176LQFP

STM32F407IGT6

Manufacturer Part Number
STM32F407IGT6
Description
IC MCU 32BIT 1MB FLASH 176LQFP
Manufacturer
STMicroelectronics
Datasheets

Specifications of STM32F407IGT6

Core Processor
ARM Cortex-M4
Core Size
32-Bit
Speed
168MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
140
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 24x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Core
ARM Cortex M4
Processor Series
STM32F4
Data Bus Width
32 bit
Maximum Clock Frequency
168 MHz
Data Ram Size
192 KB
On-chip Adc
Yes
Number Of Programmable I/os
140
Number Of Timers
10
Operating Supply Voltage
1.7 V to 3.6 V
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, I2C, I2S, SPI, UART
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-11604

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Pinouts and pin description
Table 5.
1. Function availability depends on the chosen device.
2. The functions in bold are remapped through peripheral registers.
3. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
6. If the device is delivered in an UFBGA176 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode),
48/154
55
56
57
58
59
60
61
62
63
64
-
-
-
-
-
-
-
-
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a
maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F46x reference manual, available from the STMicroelectronics website:
www.st.com.
then PA0 is used as an internal Reset (active low).
100 144
89
90
91
92
93
94
95
96
97
98
99
-
-
-
-
-
-
132
133
134
135
136
137
138
139
140
141
142
143
Pins
-
-
-
-
-
STM32F40x pin and ball definitions (continued)
A10
B7
A9
A6
B6
B5
D6
A5
B4
A4
A3
D5
C6
C5
D4
C4
C3
C2
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
-
Pin name
PDR_ON
BOOT0
PG15
V
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
PE1
V
PI4
PI5
PI6
PI7
SS_3
DD
Doc ID 022152 Rev 1
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
Function
TRACESWO
PDR_ON
NJTRST
BOOT0
JTDO/
PG15
V
reset
PB5
PB6
PB7
PB8
PB9
PE0
PE1
V
PI4
PI5
PI6
PI7
SS_3
DD
(1)
after
JTDO/ TRACESWO/ SPI3_SCK / I2S3_CK / TIM2_CH2 /
ETH_PPS_OUT/TIM3_CH2 / SPI1_MOSI/ SPI3_MOSI /
OTG_FS_SCL/ ETH_MII_TXD3 / I2C1_SCL/ CAN1_RX
I2C1_SDA / FSMC_NL / DCMI_VSYNC / USART1_RX/
I2C1_SCL/ TIM4_CH1 / CAN2_TX /OTG_FS_INTN /
OTG_FS_SDA/ SDIO_D5 / DCMI_D7 / I2C1_SDA /
NJTRST/ SPI3_MISO / TIM3_CH1 / SPI1_MISO /
SPI2_NSS/ I2S2_WS / TIM4_CH4/ TIM11_CH1/
TIM4_CH3/SDIO_D4/ TIM10_CH1 / DCMI_D6 /
I2C1_SMBA/ CAN2_RX / OTG_HS_ULPI_D7 /
TIM4_ETR / FSMC_NBL0 / DCMI_D2
USART6_CTS / DCMI_D13
TIM8_CH1 / DCMI_VSYNC
STM32F405xx, STM32F407xx
FSMC_NBL1 / DCMI_D3
DCMI_D5/USART1_TX
TIM8_BKIN / DCMI_D5
Alternate functions
TIM8_CH2 / DCMI_D6
TIM8_CH3 / DCMI_D7
DCMI_D10 / I2S3_SD
I2S3ext_SD
TIM4_CH2
SPI1_SCK
CAN1_TX
V
PP
(2)

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