LPC1342FHN33,518 NXP Semiconductors, LPC1342FHN33,518 Datasheet - Page 21

• Manufacturer Part Number: LPC1342FHN33,518
• Description: IC MCU 32BIT 16KB FLASH 32HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,518

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1311_13_42_43
Product data sheet
7.12.1 Features
7.13.1 Features
7.14.1 Features
7.13 10-bit ADC
7.14 General purpose external event counter/timers
The LPC1311/13/42/43 contains one ADC. It is a single 10-bit successive approximation
ADC with eight channels.
The LPC1311/13/42/43 includes two 32-bit counter/timers and two 16-bit counter/timers.
The counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
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The I
pins. The I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
The I
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to V
10-bit conversion time ≥ 2.44 μs (up to 400 kSamples/s).
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or timer match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
A 32-bit/16-bit counter/timer with a programmable 32-bit/16-bit prescaler.
Counter or timer operation.
One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.
2
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2
C-bus interface is a standard I
C-bus can be used for test and diagnostic purposes.
C-bus controller supports multiple address recognition and a bus monitor mode.
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C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 10 August 2010
DD
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2
C-bus compliant interface with true open-drain
32-bit ARM Cortex-M3 microcontroller
LPC1311/13/42/43
© NXP B.V. 2010. All rights reserved.
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