LPC1787FBD208,551 NXP Semiconductors, LPC1787FBD208,551 Datasheet - Page 2
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LPC1787FBD208,551
Manufacturer Part Number
LPC1787FBD208,551
Description
IC MCU 32BIT 512KB FLASH 208LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheet
1.LPC1774FBD208551.pdf
(117 pages)
Specifications of LPC1787FBD208,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
165
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-7575
LPC1787FBD208,551
LPC1787FBD208,551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1787FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC178X_7X
Objective data sheet
Memory:
LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistors (TFT) displays.
External Memory Controller (EMC) provides support for asynchronous static memory
devices such as RAM, ROM and flash, as well as dynamic memories such as single
data rate SDRAM.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, GPIO, and for
memory-to-memory transfers.
Serial interfaces:
Cortex-M3 system tick timer, including an external clock input option.
Standard JTAG test/debug interface as well as Serial Wire Debug and Serial
WireTrace Port options.
Emulation trace module supports real-time trace.
Boundary scan for simplified board testing.
Non-maskable Interrupt (NMI) input.
512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. The combination of an enhanced
flash memory accelerator and location of the flash memory on the CPU local
code/data bus provides high code performance from flash.
96 kB on-chip SRAM includes:
64 kB of SRAM on the CPU with local code/data bus for high-performance CPU
access.
Two 16 kB SRAM blocks with separate access paths for higher throughput. These
SRAM blocks may be used for DMA memory as well as for general purpose
instruction and data storage.
4032 byte on-chip EEPROM.
Dedicated DMA controller.
Selectable display resolution (up to 1024 768 pixels).
Supports up to 24-bit true-color mode.
Ethernet MAC with MII/RMII interface and associated DMA controller. These
functions reside on an independent AHB.
USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and
associated DMA controller.
Five UARTs with fractional baud rate generation, internal FIFO, DMA support, and
RS-485/EIA-485 support. One UART (UART1) has full modem control I/O, and one
UART (USART4) supports IrDA, synchronous mode, and a smart card mode
conforming to ISO7816-3.
Three SSP controllers with FIFO and multi-protocol capabilities. The SSP
interfaces can be used with the GPDMA controller.
Three enhanced I
the full I
with standard port pins. Enhancements include multiple address recognition and
monitor mode.
I
the GPDMA.
2
S (Inter-IC Sound) interface for digital audio input or output. It can be used with
2
C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 27 May 2011
2
C-bus interfaces, one with a true open-drain output supporting
32-bit ARM Cortex-M3 microcontroller
LPC178x/7x
© NXP B.V. 2011. All rights reserved.
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