SI2110-D-FMR Silicon Laboratories Inc, SI2110-D-FMR Datasheet
SI2110-D-FMR
Specifications of SI2110-D-FMR
Related parts for SI2110-D-FMR
SI2110-D-FMR Summary of contents
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ELLI TE ECEIVER FOR Q L UICK OCK AND Features Single-chip tuner, demodulator, and LNB controller DVB-S and DSS compliant QPSK/BPSK demodulation Integrated step-up dc-dc converter for LNB power supply (Si2108/10 only) Input signal level: –82 to ...
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Si2107/08/09/10 2 Rev. 1.0 ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si2107/08/09/10 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient temperature DC supply voltage 3 supply voltage 1.8 V Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Table 2. Absolute ...
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Table 3. DC Characteristics (V = 3.3 V ±10 1.8 V ±5%, T 3.3 1.8 Parameter Supply current 3.3 V Supply current 1.8 V Input high voltage Input low voltage 2 Input leakage Output high voltage Output low ...
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Si2107/08/09/10 Table 5. Receiver Characteristics Parameter Symbol RF Input frequency range Fine tune step size Symbol rate range Carrier offset correction range Carrier lock/acquisition times with QuickLock *Note: For signal with C/N = 8.5 dB Pin = –40 dBm, Channel ...
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Table 6. LNB Supply Characteristics (Si2108/10 Only) Parameter Supply voltage Converter switch frequency Output HIGH voltage Output LOW voltage Low to high transition time High to low transition time Line regulation Load regulation Load capacitance tolerance Output current limiting Peak ...
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Si2107/08/09/10 2 Table Bus Characteristics Parameter SCL clock frequency Bus free time between START and STOP condition Hold time (repeated) START condition. (After this period, the first clock pulse is generated.) LOW period of SCL clock HIGH ...
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Table 8. MPEG-TS Specifications (Rising Launch and Capture) Parameter Symbol Clock cycle time t cycle Clock low time t clow Clock high time t chigh Hold time t hold Setup time t setup Access time t access L TS_CLK TS_DATA ...
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Si2107/08/09/10 Table 9. MPEG-TS Specifications (Rising Launch, Falling Capture) Parameter Symbol Clock cycle time t cycle Clock low time t clow Clock high time t chigh Hold time t hold Setup time t setup Access time t access L TS_CLK ...
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Input Power (dBm) Figure 4. Eb/No (QEF Operation) vs. Input Power for Si2107/08/09/10 (Typical 27.5 MBaud 7/8 1 0.1 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 ...
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Si2107/08/09/10 Figure 6. Phase Noise Performance for Si2107/08/09/10 (Typical) 0.3 0.25 0.2 0.15 0.1 0.05 0 -10 Frequency Offset of Desired Channel (MHz) Figure 7. Frequency Offset vs. Carrier Lock/Acquisition Time for Various Baudrates Using QuickLock ...
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Typical Application Schematics 2 VDD_LNA XTAL1 1 35 REXT XTAL2 2 34 ADDR VDD_XTAL 3 33 VDD_MIX XTOUT 4 32 VDD_BB VDD_PLL33 5 31 VDD_ADC INT/RLK/GPO 6 30 TDET/VSEN TS_ERR 7 29 TGEN/LNB1 TS_VAL 8 28 NC/ISEN TS_SYNC 9 ...
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... Si2107/08/09/10 14 Si2110 LNB Control Si2110 LNB Control Rev. 1.0 ...
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... Si2110 LNB Control Si2110 LNB Control Rev. 1.0 Si2107/08/09/10 15 ...
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Si2107/08/09/10 3. Bill of Materials Table 10. Si2107/08/09/10 Bill of Materials Component C1,C2,C4,C6,C10,C8,C9,C13,C14, C15,C16 C5 C3,C7,C11,C12 C19,C36 TC1 Notes: 1. Transient voltage suppression device should be selected to match the surge requirements of ...
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Table 11. DiSEqC 1.x LNB Supply Bill of Materials (Si2108/10 Only) Component C30 47 µ Electrolytic,± 20% C31 C32 C33 C34 D1 ZHCS750TA 750 mA D3 MMBD1705, Dual diode DR78098, 33 ...
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Si2107/08/09/10 Table 12. DiSEqC 2.x LNB Supply Bill of Materials (Si2108/10 Only) Component C17 C30 C31,C35 C32 C33 C34 Q3,Q5, R10 R11 R12,R20 R13 R14 R15 R16 R17 ...
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... Si2107 and Si2109 can be used; these do not integrate the LNB step-up dc-dc controller. On the other hand, the Si2109 and Si2110 integrate an on-chip “blindscan” accelerator, QuickScan, which allows the implementation of a very fast channel scan, an important feature for end products targeted to free- to-air (FTA) applications in which channel frequencies and symbol rates are unknown ...
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Si2107/08/09/10 5.2. Demodulator The demodulator supports QPSK demodulation of channels between Mbaud. It incorporates the following functional blocks: analog-to- digital converters (ADCs), dc notch filters, I/Q imbalance corrector, decimation filters, matched filters, equalizer, digital automatic gain controls, ...
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On-Chip LNB DC-DC Step-Up Controller (Si2108/10 Only) Next to the LNB message signaling controller, the device also integrates the LNB supply regulator controller. The supported LNB architecture consists of a step-up dc-dc (boost) converter followed by an efficient filter, ...
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Si2107/08/09/10 In serial mode, the transport stream clock rate range is determined by the TSSCR register. The exact rate is determined during the acquisition process. The range that minimizes the difference between the effective transport stream data rate and the ...
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Continuous Parallel Data Mode :TSM = 1, TSCM = 1, TSPG = 0 TS_CLK, rising edge TS_DATA[7:0] TS1 (sync) TS_SYNC, active high TS_VAL, active high TS_ERR, active high Continuous Parallel Data Mode :TSM = 1, TSCM = 1,TSPG = 1 ...
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Si2107/08/09/10 Continuous Serial Data Mode: TSM = 0, TSCM = 1, TSPG = 0 TS_CLK, rising edge+ TS1 (sync) TS_DATA[0] TS_SYNC, active low 1-bit wide TS_VAL, active low TS_ERR, active low Continuous Serial Data Mode: TSM = 0, TSCM = ...
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Interrupts The device is equipped with several sticky interrupt bits to provide precise event tracking and monitoring. Next to interrupts being signaled via the I map, the user can program one of the device terminals (INT dedicated ...
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Si2107/08/09/10 Table 16. Events, Interrupts, and Status Bits (Continued) Blindscan done Blindscan data ready 26 BSDO_I BSDO_E BSDA_I BSDA_E Rev. 1.0 BSDO BSDA ...
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Receiver Status During receive operation, the host can retrieve information on the status of AGC lock (AGCL), carrier estimation lock (CEL), symbol rate estimation lock (SRL), symbol timing lock (STL), carrier recovery lock (CRL), Viterbi decoder lock (VTL), frame ...
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Si2107/08/09/10 In legacy mode, seven different carrier offset estimation search range scans can be programmed from 0.10 to ~6.0 MHz with register CESR. This mode locates frequency offsets when the carrier falls within the offset search range. Smaller search ranges ...
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Calibration LO Tuning Analog AGC Search Fail Done CFO Estimation Done Unlock Symbol Timing Loop lock Unlock Carrier Frequency Loop Unlock lock Viterbi Search (Limited) Unlock lock Frame Search lock Unlock Receiver locked Figure 15. Fade Recovery Sequence Si2107/08/09/10 6.4.6. ...
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Si2107/08/09/10 6.5.3. Reed-Solomon Error Monitor The Reed-Solomon error monitor is capable of counting bit, byte, and uncorrectable packet errors. The error type to be counted is controlled by the Reed-Solomon error type register, RSERT. The Reed-Solomon error mode bit, RSERM, ...
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When gain adjustments are made, the device allows up to 100 µs for the gain changes to settle before beginning the next measurement. To facilitate a rapid initial acquisition, Si2107/08/09/10 includes an acquisition mode wherein the measurement window size is ...
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Si2107/08/09/10 6.7. LNB Signaling Controller All device versions provide LNB signaling capability. The device supports several LNB signaling methods including dc voltage selection, continuous tone, tone burst, DiSEqC 1.x- and DiSEqC messaging. A description of each method follows. 6.7.1. DC ...
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The message length must also be reprogrammed to indicate how many more bytes remain to be sent. The interval between FIFO reads is typically 13.5 ms. To support cascaded DiSEqC devices, it may be necessary to repeat ...
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... On-Chip LNB DC-DC Step-Up Controller (Si2108/10 Only) In addition to the LNB signaling controller present on all device versions, Si2108 and Si2110 devices contain an internal supply controller circuit. This internal dc-dc controller can be enabled via register bit LNB_EN. The internal circuit requires the connection of an external ...
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The LNB supply controller is disabled by default. To use the supply, it must be enabled by setting the LNB enable bit, LNB_EN. If the LNB supply circuit is connected, the TFS bit is ignored; the internal LNB supply controller ...
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Si2107/08/09/10 tolerance level for determination of the 1 dB bandwidth for a detected channel Bandwidth Threshold Register. This sets the tolerance level for determination of the 2 dB bandwidth for a detected channel Bandwidth ...
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I C Control Interface 2 The I C bus interface is provided for configuration and monitoring of all internal registers. The Si2107/08/09/10 supports the 7-bit addressing procedure and is capable of operating at rates up to 400 kbps. ...
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... Unused register bits of a register byte are reserved, Their bit values should not be changed from the default values, as identified below under the description of each individual register byte. Table 18 lists all registers available in Si2110; some registers may not be available in other part versions, as identified below under the description of each individual register byte. ...
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Table 19. Register Summary (Continued) Name Addr. Acq Ctrl 1 14h AQS ADC SR 15h Coarse Tune 16h Fine Tune L 17h Fine Tune H 18h CE Ctrl 29h CE Offset L 36h CE Offset H ...
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Si2107/08/09/10 Table 19. Register Summary (Continued) Name Addr. AGC Ctrl 1 23h AGC Ctrl 2 24h AGC 1–2 Gain 25h AGC 3–4 Gain 26h AGC TH 27h AGC PL 28h DAGC 1 Ctrl 75h DAGC1_EN DAGC1 ...
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Name Addr. Host Ctrl 1Ch SR Est L 31h SR Est M 32h SR Est H 33h SR Est Ctrl 2 3Ah SR Max 42h SR Min 43h BS Ctrl 80h BS_ START BS MinFreq L ...
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... Name 0 PDE Bit Name 7 Reserved 6 PDE 5 INC_DS 4:3 MOD[1:0] 2:0 SYSM[2: Function Device ID Si2110 1h = Si2109 2h = Si2108 3h = Si2107 Revision. Current revision = INC_DS MOD[1:0] Function Program as shown above. Sleep Mode Disabled (default): normal operation 1 = Enabled Automatic Address Increment Disable Enabled (default Disabled Modulation Selection. ...
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Register 02h. Transport Stream Control 1 Bit D7 D6 Name TSEP TSVP Bit Name 7 TSEP 6 TSVP 5 TSSP 4 TSSL 3 TSCM 2 TSCE 1 TSDF 0 TSM TSSP TSSL TSCM Function Transport Stream Error ...
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Si2107/08/09/10 Register 03h. Transport Stream Control 2 Bit D7 D6 Name 0 Bit Name 7:6 Reserved 5 TSPCS 4 TSCD 3 TSDD 2 TSPG 1:0 TSSCR[1: TSPCS TSCD TSDD Function Program as shown above. Transport Stream ...
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Register 04h. Pin Control Bit INT_EN INTT Name Bit Name 7 INT_EN 6 INTT 5 INTP 4 TSE_OE 3 TSV_OE 2 TSS_OE 1 TSC_OE 0 TSD_OE INTP TSE_OE TSV_OE Interrupt Pin Enable ...
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Si2107/08/09/10 Register 05h. Pin Control 2 Bit D7 D6 Name 0 0 Bit Name 7:3 Reserved 2 GPO 1:0 PSEL[1:0] Register 06h. Bypass Bit D7 D6 Name 0 0 Bit Name 7:6 Reserved 5 DS_BP 4 RS_BP 3 DI_BP 2:0 ...
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Register 07h. Interrupt Enable 1 Bit D7 D6 Name RCVL_E AGCL_E Bit Name 7 RCVL_E 6 AGCL_E 5 CEL_E 4 Reserved 3 STL_E 2 CRL_E 1 VTL_E 0 FSL_E CEL_E 0 STL_E Function Receiver Lock Interrupt Enable. ...
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Si2107/08/09/10 Register 08h. Interrupt Enable 2 Bit D7 D6 Name RCVU_E AGCTS_E Bit Name 7 RCVU_E 6 AGCTS_E 5 STU_E 4 CRU_E 3 VTU_E 2 FSU_E 1 Reserved 0 AQF_E STU_E CRU_E VTU_E FSU_E Function Receiver ...
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Register 09h. Interrupt Enable 3 Bit D7 D6 Name CN_E VTER_E RSER_E Bit Name 7 CN_E 6 VTER_E 5 RSER_E 4 MSGPE_E 3 FE_E 2 FF_E 1 MSGR_E 0 MSGTO_E MSGPE_E FE_E Function C/N Estimator Interrupt Enable. ...
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Si2107/08/09/10 Register 0Ah. Interrupt Enable 4 Bit D7 D6 Part Name 0 0 Part Name 0 BSDO_E Bit Name 7 Reserved 6 BSDO_E 5 BSDA_E 4:2 Reserved 1 SCD_E 0 OCD_E Si2107 Si2109/10 ...
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Register 0Bh. Interrupt Status 1 Bit D7 D6 Name RCVL_I AGCL_I Bit Name 7 RCVL_I 6 AGCL_I 5 CEL_I 4 Reserved 3 STL_I 2 CRL_I 1 VTL_I 0 FSL_I CEL_I 0 STL_I Function Receiver Lock Interrupt. 0 ...
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Si2107/08/09/10 Register 0Ch. Interrupt Status 2 Bit D7 D6 RCVU_I AGCTS_I Name Bit Name 7 RCVU_I 6 AGCTS_I 5 STU_I 4 CRU_I 3 VTU_I 2 FSU_I 1 Reserved 0 AQF_I STU_I CRU_I VTU_I FSU_I Function Receiver ...
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Register 0Dh. Interrupt Status 3 Bit D7 D6 Name CN_I VTER_I Bit Name 7 CN_I 6 VTER_I 5 RSER_I 4 MSGPE_I 3 FE_I 2 FF_I 1 MSGR_I 0 MSGTO_I RSER_I MSGPE_I FE_I Function C/N Estimator Interrupt. 0 ...
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Si2107/08/09/10 Register 0Eh. Interrupt Status 4 Bit D7 D6 Part Name 0 0 Part Name 0 BSDO_I Bit Name 7 Reserved 6 BSDO_I 5 BSDA_I 4:2 Reserved 1 SCD_I 0 OCD_I Si2107 Si2109/10 ...
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Register 0Fh. Lock Status 1 Bit AGCL Name Bit Name 7 Reserved 6 AGCL 5 CEL 4 SRL 3 STL 2 CRL 1 VTL 0 FSL CEL SRL STL Function Program as shown above. ...
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Si2107/08/09/10 Register 10h. Lock Status 2 Bit D7 D6 Part Name RCVL 0 Part Name RCVL 0 Bit Name 7 RCVL 6:2 Reserved 1 BSDA 0 BSDO Si2107 Si2109/ Function ...
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Register 11h. Acquisition Status Bit D7 D6 Name AQF AGCF Bit Name 7 AQF 6 AGCF 5 CEF 4 SRF 3 STF 2 CRF 1 VTF 0 FSF CEF SRF STF Function Receiver Acquisition Status ...
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Si2107/08/09/10 Register 14h. Acquisition Control 1 Bit D7 D6 Name AQS 0 Bit Name 7 AQS 6:0 Reserved Register 15h. ADC Sampling Rate Bit D7 D6 Name Bit Name 7:0 ADCSR[7:0] Register 16h. Coarse Tune Frequency Bit D7 D6 Name ...
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Register 17h. Fine Tune Frequency L Bit D7 D6 Name Bit Name 7:0 FTF[7:0] Register 18h. Fine Tune Frequency H Bit D7 D6 Name 0 Bit Name 7 Reserved 6:0 FTF[14: FTF[7:0] Function Fine Tune Frequency (Low ...
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... Si2107/08/09/10 Register 1Ch. Host Control Register (Si2109 and Si2110 only) Bit Name Bit Name 7:4 Reserved 3 SR_CTRL_HOST 2 ADCSR_CTRL_HOST 1 CTF_CTRL_HOST 0 FTF_CTRL_HOST Register 23h. Analog AGC Control 1 Bit D7 D6 Name 0 0 Bit Name 7:6 Reserved 5:4 AGCW[1:0] 3:0 Reserved SR_ CTRL_ ADCSR_CTRL_ HOST ...
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Register 24h. AGC Control 2 Bit D7 D6 Name AGCTR[3:0] Bit Name 7:4 AGCTR[3:0] 3:0 AGCO[3:0] Register 25h. Analog AGC 1–2 Gain Bit D7 D6 Name AGC2[3:0] Bit Name 7:4 AGC2[3:0] 3:0 AGC1[3:0] Register 26h. Analog AGC 3–4 Gain Bit ...
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Si2107/08/09/10 Register 27h. AGC Threshold Bit D7 D6 Name 0 Bit Name 7 Reserved 6:0 AGCTH[6:0] Register 28h. AGC Power Level D7 D6 Bit 0 Name Bit Name 7 Reserved 6:0 AGCPWR[6: AGCTH[6:0] Function Program as ...
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... Bit Name 7:3 Reserved 2:0 CESR[2:0] Register 31h. Symbol Rate Estimator Register L (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 SREST[7:0] Register 32h. Symbol Rate Estimator Register M (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 SREST[15: Function Program as shown above ...
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... Si2107/08/09/10 Register 33h. Symbol Rate Estimator Register H (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 SREST[23:16] Register 36h. Carrier Estimator Offset Bit Name Bit Name 7:0 CFO[7: SREST[23:16] Function Symbol Rate Estimate (High Byte). See register 31h. Default: 00h ...
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Register 37h. Carrier Estimator Offset Bit Name Bit Name 7:0 CFO[15:8] Register 38h. Carrier Frequency Offset Error Bit Name Bit Name 7:0 CFER[7:0] Register 39h. Carrier Frequency Offset Error H Bit D7 D6 Name ...
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Si2107/08/09/10 Register 3Ah. Symbol Rate Estimator Control 2 Register Bit Name Bit Name 7:1 Reserved 0 FALSE_ALARM_PROC_EN Register 3Fh. Symbol Rate L Bit D7 D6 Name Bit Name 7:0 SR[7:0] Register 40h. Symbol Rate ...
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... Name Bit Name 7:0 SR[23:16] Register 42h. Symbol Rate Maximum (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 SRMAX[7:0] Register 43h. Symbol Rate Minimum (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 SRMIN[7: SR[23:16] Function Symbol Rate (High Byte). ...
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Si2107/08/09/10 Register 75h. Digital AGC 1 Control Bit D7 D6 Name 0 DAGC1_EN Bit Name 7 Reserved 6 DAGC1_EN 5:4 DAGC1W[1:0] 3 DAGC1T 2 DAGC1HOLD 1 DAGC1HOST 0 Reserved Register 76h. Digital AGC 1 Gain L Bit D7 D6 Name ...
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Register 77h. Digital AGC 1 Gain H Bit D7 D6 Name Bit Name 7:0 DAGC1[15:8] Register 78h. Digital AGC 2 Control Bit D7 D6 Name Reserved Bit Name 7 Reserved 6:3 DAGC2[3:0] 2:1 DAGC2W[1:0] 0 DAGC2TDIS Register 79h. Digital AGC ...
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Si2107/08/09/10 Register 7Ah. Digital AGC 2 Level L Bit D7 D6 Name Bit Name 7:0 DAGC2GA[7:0] Register 7Bh. Digital AGC 2 Level H Bit D7 D6 Name Bit Name 7:0 DAGC2GA[15:8] Register 7Ch. C/N Estimator Control Bit D7 D6 Name ...
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Register 7Dh. C/N Estimator Threshold0 Bit D7 D6 Name Bit Name 7:0 CNET[7:0] Register 7Eh. C/N Estimator Level L Bit D7 D6 Name Bit Name 7:0 CNL[7:0] Register 7Fh. C/N Estimator Level H Bit D7 D6 Name Bit Name 7:0 ...
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... Bit D7 D6 BS_START Name 0 Bit Name 7 BS_START 6 Reserved 5 BSDA 4:1 Reserved 0 COESM Register 81h. QuickScan Controller Minimum Frequency Register L (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 BS_FMIN[7:0] Lower RF frequency limit for QuickScan range: Default: 14h BSDA 0 0 Function QuickScan Start ...
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... Bit Name 7:2 Reserved Program as shown above. 1:0 BS_FMIN[17:16] See register 81h. Default: 01h Register 84h. QuickScan Controller Maximum Frequency Register L (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 BS_FMAX[7:0] Higher RF frequency limit for QuickScan range: Default: F6h ...
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... Bit D7 D6 Name Bit Name 7:0 BS_CTF[7:0] Coarse frequency of identified channel = 10 MHz x BS_CTF. Default: 00h Register 8Ah. QuickScan Controller Fine Tuning Frequency Register L (Si2109 and Si2110 only Bit Name Bit Name 7:0 BS_FTF[7:0] Fine frequency of identified channel, low byte. Fine frequency = BS_Fs/16384 x BS_FTF ...
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... Register 8Bh. QuickScan Controller Fine Tuning Frequency Register H (Si2109 and Si2110 only) Bit D7 D6 Name 0 Bit Name 7 Reserved Program as shown above. 6:0 BS_FTF[14:8] Fine frequency of identified channel, high byte. See register 8Ah. Default: 00h Register 8Ch. QuickScan Controller ADC Sampling Rate Register (Si2109 and Si2110 only) ...
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... Si2107/08/09/10 Register 8Fh. Spectrum Tilt Correction Threshold Register (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 SPEC_TILT_CORREC[7:0] Correction to be applied for spectrum tilt. Register 90h. 1dB Bandwidth Threshold Register (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 BW_1dB[7:0] Register 91h ...
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... Threshold for determining the drop in power in a channel as the LSA scans a THRESHOLD[7:0] detected channel to determine the channel bandwidth. Refer to Silicon Laboratories application note AN298 for recommended default val- ues for QuickLock/QuickScan operation. Register 94h. Noise Level Margin Threshold Register (Si2109 and Si2110 only) Bit D7 D6 Name ...
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Si2107/08/09/10 Register A2h. Viterbi Search Control 2 Bit D7 D6 Name 0 0 Bit Name 7:4 Reserved 3 VTERS 2 VTERM 1:0 VTERW[1:0] Register A3h. Viterbi Search Status Bit D7 D6 VTRS[2:0] Name Bit Name 7:5 VTRS[2:0] 4:2 Reserved 1 ...
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Register ABh. Viterbi BER Count L Bit D7 D6 Name Bit Name 7:0 VTERC[7:0] Register ACh. Viterbi BER Count H Bit D7 D6 Name Bit Name 7:0 VTERC[15: VTERC[7:0] Function Viterbi BER Counter (Low Byte). Stores the ...
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Si2107/08/09/10 Register B0h. Reed-Solomon BER Error Monitor Control Bit D7 D6 Name 0 0 Bit Name 7:5 Reserved 4 RSERS 3 RSERM 2 RSERW 1:0 RSERT[1:0] Register B1h. Reed-Solomon Error Monitor Count Bit Name Bit Name 7:0 ...
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Register B2h. Reed-Solomon Error Monitor Count H Bit D7 D6 Name Bit Name 7:0 RSERC[15:8] Register B3h. Descrambler Control Bit D7 D6 Name 0 0 Bit Name 7:2 Reserved 1 DST_DS 0 DSO_DS RSERC[15:8] Function Reed-Solomon Error ...
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Si2107/08/09/10 Register B5h. PRBS Control Bit D7 D6 Name PRBS_START PRBS_INVERT PRBS_SYNC Bit Name 7 PRBS_START 6 PRBS_INVERT 5 PRBS_SYNC 4:2 Reserved 1:0 PRBS_HEADER_SIZE Function Start PRBS Synchronization Start PRBS synchronization Default ...
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Register C0h. LNB Control 1 Bit D7 D6 Part LNBS 0 Name Part LNBS LNBV Name Bit Name 7 LNBS LNB Start. Writing a one to this bit initiates an LNB signaling sequence. This bit is automatically cleared to zero ...
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Si2107/08/09/10 Register C1h. LNB Control 2 Bit D7 D6 Name LNBM[1:0] Bit Name 7:6 LNBM[1:0] 5:3 Reserved 2 BRST_DS 1 TFS 0 Reserved Register C2h. LNB Control 3 Bit Name TDIR TT TR Bit Name 7 TDIR ...
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Register C3h. LNB Control 4 Bit D7 D6 Name Bit Name 7 TFQ[7: TFQ[7:0] Function LNB Tone Frequency Control. Used to set the frequency of the LNB tone according to the following equation: Frequency = 100 MHz/[32 ...
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Si2107/08/09/10 Register C4h. LNB Status Bit D7 D6 Name FE FF Bit Name MSGPE 4 MSGR 3 MSGTO 2:0 MSGRL[2: MSGPE MSGR MSGTO Function Message FIFO Empty Normal operation ...
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... Register C5-CAh. Message FIFO 1–6 Bit D7 D6 Name Bit Name 7:0 FIFO1–6[7:0] Register CBh. LNB Supply Control 1 (Si2108 and Si2110 only) Bit D7 D6 Name VLOW[3:0] Bit Name 7:4 VLOW[3:0] 3:0 VHIGH[3: FIFOx[7:0] Function Message FIFO. Contains message to be transmitted or message received. ...
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... Bit D7 D6 Name ILIM[1:0] Bit Name 7:6 ILIM[1:0] 5:4 IMAX[1:0] 3:2 SLOT[1:0] 1:0 OLOT[1:0] Note: This register byte is read-only if LNBL=1. Register CDh. LNB Supply Control 3 (Si2108 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 VMON[7: IMAX[1:0] SLOT[1:0] Function Average Current Limit. ...
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... Register CEh. LNB Supply Control 4 (Si2108 and Si2110 only) Bit D7 D6 Name LNBL 0 Bit Name 7 LNBL 6:4 Reserved 3 LNB_EN 2 COMP 1 Reserved 0 LNBMD Register CFh. LNB Supply Status (Si2108 and Si2110 only) Bit D7 D6 Name 0 0 Bit Name 7:2 Reserved 1 SCD 0 OCD ...
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Si2107/08/09/10 9. Pin Descriptions Si2108/ VDD_LNA GND 2 REXT 3 ADDR VDD_MIX 4 VDD_BB 5 Top VDD_ADC 6 VSEN/TDET 7 View LNB1/TGEN 8 ISEN 9 LNB2/DRC 10 RESET 11 PWM/DCS 12 GND VDD_DIG18 13 14 ...
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Pin # Name I/O PWM/DC Voltage Select. PWM (Si2108/10 only)—Connected to gate of power MOSFET for LNB supply cir- 12 PWM/DCS O cuit. DCS—Outputs signal to indicate 18 V (HIGH (LOW) LNB supply voltage selection. Supply voltage. ...
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... Si2107/08/09/10 * 10. Ordering Guide Ordering Part # Si2110-D-FM Satellite receiver for DVB-S/DSS with LNB step-up dc-dc controller and on-chip blindscan accelerator, Pb-free and RoHS Compliant Si2109-D-FM Satellite receiver for DVB-S/DSS with on-chip blindscan accelerator, Pb-free and RoHS Compliant Si2108-D-FM Satellite receiver for DVB-S/DSS with step-up dc-dc controller, Pb- ...
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... Package Outline: 44-pin QFN Figure 23 illustrates the package details for the Si2110. Table 20 lists the values for the dimensions shown in the illustration. Table 20. Package Diagram Dimensions Millimeters Dimension Min Nom A 0.80 0.90 A1 0.00 0.02 b 0.18 0.25 D 6.00 BSC. D2 2.70 2.80 e 0.50 BSC. ...
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Si2107/08/09/10 12. PCB Land Pattern 94 Figure 24. PCB Land Pattern Rev. 1.0 ...
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Table 21. PCB Land Pattern Dimensions Dimension Notes - General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI ...
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Si2107/08/09/ OTES 96 Rev. 1.0 ...
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Si2107/08/09/ OCUMENT HANGE IST Revision 0.4 to Revision 0.5 Package dimensions changed mm. Updated pin numbering and pin descriptions. Schematics updated interface description added. MPEG-TS timing specifications added. Revision 0.5 ...
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