MT9092AP Zarlink, MT9092AP Datasheet - Page 26

• Manufacturer Part Number: MT9092AP
• Description: Digital Telephone 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9092AP

• Package: 44PLCC
• Power Supply Type: Analog
• Typical Supply Current: 8 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

Note: Bits marked "-" are reserved bits and should be written with logic "0".
HDLC Control Register 2
HDLC Interrupt Enable Register
Intsel
Tcrci
Seven
Flrx
Fltx
Rxfrst
Txfrst
This register is used with the Interrupt Register to mask out the interrupts that are not required by the microprocessor. Interrupts that are masked out
will not produce an IRQ; however, they will set the appropriate bit in the Interrupt Register. An interrupt is disabled when the microprocessor writes
a 0 to a bit in this register. This register is cleared on power reset.
When high, this bit will cause bit 2 of the Interrupt Register to reflect a Transmit FIFO underrun (Txunder). When low, this interrupt
When high, this bit will inhibit transmission of the CRC. That is, the transmitter will not insert the computed CRC onto the bit stream
When high, this bit will enable seven bits of address recognition in the first address byte. The received address byte must have bit 0
When high, this bit will change the Rx FIFO interrupt and status level from 15 to 5 bytes, thus allowing the microprocessor more time
When high, this bit will change the Tx FIFO interrupt and status level from 4 to14 bytes, thus allowing the microprocessor more time to
When high, the Rx FIFO will be reset. This causes the receiver to be disabled until the next reception of a flag, an occurrence which
When high, the Tx FIFO will be reset. The Status Register will identify the FIFO as being empty. This bit will be reset when data is
will reflect a frame abort (FA).
after seeing the EOP tag byte. The microprocessor then has the opportunity to insert the CRC as part of the data field.
equal to 1 which indicates a single address byte is being received.
to react to interrupt conditions.
react to interrupt conditions.
resets this bit. The Status Register will identify the FIFO as being empty. However, the actual bit values of data in the Rx FIFO will not
be reset.
written to the Tx FIFO. The actual bit values of data in the Tx FIFO will not be reset..
Intsel
GA
7
7
EOPD TEOP
-
6
6
Tcrci
5
5
Seven
EOPR
4
4
Zarlink Semiconductor Inc.
TxFL
Flrx
3
3
MT9092
Under
FA/Tx
26
Fltx
2
2
Rxfrst
RxFf
1
1
ADDRESS = 05h WRITE/READ VERIFY
ADDRESS = 06h WRITE/READ VERIFY
Txfrst
Ovfl
Rx
0
0
Power Reset Value
Power Reset Value
0000 0000
0000 0000
Data Sheet