MT9092AP Zarlink, MT9092AP Datasheet - Page 17

• Manufacturer Part Number: MT9092AP
• Description: Digital Telephone 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9092AP

• Package: 44PLCC
• Power Supply Type: Analog
• Typical Supply Current: 8 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

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C-Channel
Access to the internal control and status registers of Zarlink basic rate, layer 1, transceivers is through the ST-BUS
Control Channel (C-Channel), since direct microport access is not usually provided, except in the case of the SNIC
(MT8930). The HPhone-II provides asynchronous microport access to the ST-BUS C-Channel information on both
DSTo and DSTi via a double-buffered read/write register (address 14h). Data written to this address is transmitted
on the C-Channel every frame when enabled by CH
LCD
A twelve segment, non-multiplexed, LCD display controller is provided for easy implementation of various set status
and call progress indicators. The twelve output pins (S
located in LCD Segment Enable Registers 1&2 (addresses 12h and 13h), and the BackPlane output pin (BP) to
control the on/off state of each segment individually.
The BP pin drives a continuous 62.5 Hz, 50% duty cycle squarewave output signal. An individual segment is
controlled via the phase relationship of its segment driver output pin with respect to the backplane, or common,
driver output. Each of the twelve Segment Enable bits corresponds to a segment output pin. The waveform at each
segment pin is in-phase with the BP waveform when its control bit is set to logic zero (segment off) and is out-of-
phase with the BP waveform when its control bit is set to a logic high (segment on). Refer to the LCD Driver
Characteristics for pin loading information.
Microport
A serial microport, compatible with Intel MCS-51 (mode 0) specifications, provides access to all HPhone-II internal
read and write registers. This microport consists of three pins; a half-duplex transmit/receive data pin (DATA1), a
chip select pin (CS) and a synchronous data clock pin (SCLK).
The handset speaker outputs (receiver), pins HSPKR+/HSPKR-. This internally compensated, fully
differential output driver is capable of driving the load shown in Figure 5. This output is enabled/disabled by
the HSSPKR EN bit residing in the Transducer Control Register (address 0Eh). The nominal handset receive
path gain may be adjusted to either -12.3 dB (suggested for µ-Law) or -9.7 dB (suggested for A-Law).
Control of this gain is provided by the RxA/u control bit (General Control Register, address 0Fh). This gain
adjustment is in addition to the programmable gain provided by the receive filter and DSP.
The loudspeaker outputs, pins SPKR+/SPKR-. This internally compensated, fully differential output driver is
capable of directlydriving 6.5 vpp into a 40 ohm load. This output is enabled/disabled by the SPKR EN bit
residing in the Transducer Control Register (address 0Eh). The nominal gain for this amplifier is 0.2 dB.
HSPKR+
HSPKR-
MT9092
Figure 5 - Handset Speaker Driver
Zarlink Semiconductor Inc.
MT9092
1
EN (see ST-BUS/Timing Control).
75 Ω
75 Ω
17
n
) are used in conjunction with 12 segment control bits,
1000 pF
1000 pF
ground
150 ohm
(speaker)
load
Data Sheet