MT9092AP Zarlink, MT9092AP Datasheet - Page 11

• Manufacturer Part Number: MT9092AP
• Description: Digital Telephone 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9092AP

• Package: 44PLCC
• Power Supply Type: Analog
• Typical Supply Current: 8 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

Frame Checking Sequence Field
The 16 bits preceding a closing flag are the FCS field. A cyclic redundancy check utilizing the CRC-CCITT standard
generator polynomial X
of the address, control and information fields. The complement of the FCS is transmitted, most significant bit first, in
the FCS field. The receiver calculates the FCS on the incoming packet's address, control, information and FCS
fields and compares the result to 'F0B8'. This result verifies no transmission errors occurred. If the packet, between
flags, is also at least 32 bits in length then the address, control and information field data are entered into the
receive FIFO minus the FCS which is discarded.
Order of Bit Transmission
Address, control and information field data are entered into the transmit FIFO. This data is then transmitted and
received on the serial bus least significant bit first. The FCS is sent most significant bit first on the serial bus. Note
that it is the complement of the calculated FCS which is transmitted. The HDLC does not distinguish
ADDRESS/CONTROL/INFORMATION bytes except to determine if the packet is of minimum valid length. These
fields are transferred transparently through the FIFO's.
Data Transparency (Zero insertion/deletion)
Transparency ensures that the contents of a data packet do not imitate a flag, go-ahead, frame abort or idle
channel. The contents of a transmitted frame, between the flags, is examined on a bit-by-bit basis and a 0 bit is
inserted after all sequences of five contiguous 1 bits (including the last five bits of the FCS). Upon receiving five
contiguous 1s within a frame the receiver deletes the following 0 bit.
Invalid Frames
A frame is invalid if one of the following four conditions exists. Inserted zeros are not part of a valid bit count:
1. If the FCS pattern generated from the received data does not match the 'F0B8' pattern then the last data
2. A short frame exists if there are less than 25 bits between the flags. Short frames are ignored by the
3. Packets which are at least 25 bits in length but less than 32 bits (between the flags) are also invalid. In this
4. If a frame abort sequence is detected the packet is invalid. Some or all of the current packet will reside in the
Frame Abort
The transmitter will abort a current packet by substituting a zero followed by seven contiguous 1s in place of the
normal data. The receiver will abort upon reception of seven contiguous 1s occurring between the flags of a packet
which contains at least 26 bits.
Note that should the last receive byte before the frame abort end with contiguous 1s, these are included in the
seven 1s required for a receiver abort. This means that the location of the abort sequence in the receiver may occur
before the location of the abort sequence in the originally transmitted packet. If this happens, then the last data
written to the receive FIFO will not correspond exactly with the last byte received before the frame abort.
Interframe Time Fill and Link Channel States
When the HDLC transmitter is not sending packets it will wait in one of two states.
Interframe Time Fill: This is a continuous series of flags occurring between frames indicating that the channel
Idle:
In both cases the transmitter will exit the wait state when data is loaded into the transmit FIFO.
byte of the packet is written to the receive FIFO with a 'bad packet' indication.
receiver and nothing is written into the receive FIFO.
case the data is written to the FIFO but the last byte is tagged with a 'bad packet' indication.
receive FIFO, assuming the packet length before the abort sequence was at least 26 bits long.
An idle channel occurs when at least fifteen contiguous 1s are transmitted or received.
is active but that no data is being sent.
16
+ X
12
+X
5
+1 produces the 16-bit FCS. In the transmitter the FCS is calculated on all bits
Zarlink Semiconductor Inc.
MT9092
11
Data Sheet