CS5102A-JL Cirrus Logic Inc, CS5102A-JL Datasheet - Page 33

• Manufacturer Part Number: CS5102A-JL
• Description: ADC Single SAR 20KSPS 16-Bit Serial 28-Pin PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5102A-JL

• Package: 28PLCC
• Resolution: 16 Bit
• Sampling Rate: 20 KSPS
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial
• Input Type: Voltage
• Signal To Noise Ratio: 90(Typ) dB
• Polarity Of Input Voltage: Unipolar|Bipolar

CH1/2 - Left/Right Input Channel Select, PIN 13.
SLEEP - Sleep, PIN 28.
CODE - 2’s Complement/Binary Coding Select, PIN 16.
BP/UP - Bipolar/Unipolar Input Range Select, PIN 17.
SCKMOD - Serial Clock Mode Select, PIN 27.
OUTMOD - Output Mode Select, PIN 18.
SCLK - Serial Clock, PIN 14.
RST - Reset, PIN 2.
Analog Inputs
AIN1, AIN2 - Channel 1 and 2 Analog Inputs, PINS 19 and 24.
VREF - Voltage Reference, PIN 20.
DS45F2
Status at the end of a conversion cycle determines which analog input channel will be acquired
for the next conversion cycle. When in Free Run Mode, CH1/2 is an output, and will indicate
which channel is being sampled during the current acquisition phase.
When brought low causes the CS5101A or CS5102A to enter a power-down state. All
calibration coefficients are retained in memory, so no recalibration is needed after returning to
the normal operating mode. If using the internal crystal oscillator, time must be allowed after
SLEEP returns high for the crystal oscillator to stabilize. SLEEP should be tied high for normal
operation.
Determines whether output data appears in 2’s complement or binary format. If high, 2’s
complement; if low, binary.
When low, the CS5101A or CS5102A accepts a unipolar input range from AGND to VREF.
When high, the CS5101A or CS5102A accepts bipolar inputs from -VREF to +VREF.
When high, the SCLK pin is an input; when low, it is an output. Used in conjunction with
OUTMOD to select one of 4 output modes described in Table 2.
The status of SCKMOD and OUTMOD determine which of four output modes is utilized. The
four modes are described in Table 2.
Serial data changes status on a falling edge of this input, and is valid on a rising edge. When
SCKMOD is high SCLK acts as an input. When SCKMOD is low the CS5101A or CS5102A
generates its own serial clock at one-fourth the master clock frequency and SCLK is an output.
When taken low, all internal digital logic is reset. Upon returning high, a full calibration
sequence is initiated which takes 11,528,160 CLKIN cycles (CS5101A) or 2,882,040 CLKIN
cycles (CS5102A) to complete. During calibration, the HOLD input will be ignored. The
CS5101A or CS5102A must be reset at power-up for calibration, however; calibration is
maintained during SLEEP mode, and need not be repeated when resuming normal operation.
Analog input connections for the left and right input channels.
The analog reference voltage which sets the analog input range. In unipolar mode VREF sets
full-scale; in bipolar mode its magnitude sets both positive and negative full-scale.
CS5101A CS5102A
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