CS5102A-JL Cirrus Logic Inc, CS5102A-JL Datasheet - Page 14

• Manufacturer Part Number: CS5102A-JL
• Description: ADC Single SAR 20KSPS 16-Bit Serial 28-Pin PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5102A-JL

• Package: 28PLCC
• Resolution: 16 Bit
• Sampling Rate: 20 KSPS
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial
• Input Type: Voltage
• Signal To Noise Ratio: 90(Typ) dB
• Polarity Of Input Voltage: Unipolar|Bipolar

amplifier is then bypassed, and the capacitor ar-
ray is directly connected to the input. This is
referred to as fine-charge, during which the
charge on the array is allowed to accurately settle
to the input voltage (see Figure 10).
With a full scale input step, the coarse-charge in-
put buffer of the CS5101A will charge the
capacitor array within 1% in 650 ns. The con-
verter timing allows 6 clock cycles for coarse
charge settling time. When the CS5101A
switches to fine-charge mode, its slew rate is
somewhat reduced. In fine-charge, the CS5101A
can slew at 2 V/ s in unipolar mode. In bipolar
mode, only half the capacitor array is connected
to the analog input, so the CS5101A can slew at
4V/ s.
With a full scale input step, the coarse-charge in-
put buffer of the CS5102A will charge the
capacitor array within 1% in 3.75 s. The con-
verter timing allows 6 clock cycles for coarse
charge settling time. When in fine-charge mode,
the CS5102A can slew at 0.4 V/ s in unipolar
mode; and at 0.8 V/ s in bipolar mode.
Acquisition of fast slewing signals can be has-
tened if the voltage change occurs during or
immediately following the conversion cycle. For
instance, in multiple channel applications (using
either the device’s internal channel selector or an
external MUX), channel selection should occur
while the CS5101A or the CS5102A is convert-
ing. Multiplexer switching and settling time is
thereby removed from the overall throughput
equation.
If the input signal changes drastically during the
acquisition period (such as changing the signal
source), the device should be in coarse-charge for
an adequate period following the change. The
CS5101A and CS5102A can be forced into
coarse-charge by bringing CRS/FIN high. The
buffer amplifier is engaged when CRS/FIN is
high, and may be switched in any number of
14
times during tracking. If CRS/FIN is held low,
the CS5101A and CS5102A will only coarse-
charge for the first 6 clock cycles following a
conversion, and will stay in fine-charge until
HOLD goes low. To get an accurate sample using
the CS5101A, at least 750 ns of coarse-charge,
followed by 1.125 s of fine-charge is required
before initiating a conversion. If coarse charge is
not invoked, then up to 25 s should be allowed
after a step change input for proper acquisition.
To get an accurate sample using the CS5102A, at
least 3.75
5.625 s of fine-charge is required before initiat-
ing a conversion (see Figure 2). If coarse charge
is not invoked, then up to 125 s should be al-
lowed after a step change input for proper
acquisition. The CRS/FIN pin must be low prior
to HOLD becoming active and be held low dur-
ing conversion.
Master Clock
The CS5101A and CS5102A can operate either
from an externally-supplied master clock, or from
their own crystal oscillator (with a crystal). To
enable the internal crystal oscillator, simply tie a
crystal across the XOUT and CLKIN pins and
add 2 capacitors and a resistor, as shown on the
system connection diagram in Figure 8.
Calibration and conversion times directly scale to
the master clock frequency. The CS5101A-8 can
operate with clock or crystal frequencies up to
9.216 MHz (8.0 MHz in FRN mode). This allows
maximum throughput of up to 50 kHz per chan-
nel in dual-channel operation, or 100 kHz in a
single channel configuration. The CS5101A-16
can accept a maximum clock speed of 4 MHz,
with corresponding throughput of 50 kHz. The
CS5102A can operate with clock or crystal frequen-
cies up to 2.0 MHz (1.6 MHz in FRN mode). This
allows maximum throughput of up to 10 kHz per
channel in dual-channel operation, or 20 kHz in a
single channel configuration. For 16 bit performance
a 1.6 MHz clock is recommended. This 1.6 MHz
s of coarse-charge, followed by
CS5101A CS5102A
DS45F2