MT90840AP Zarlink, MT90840AP Datasheet - Page 30

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

If the clocks lose their phase lock, the MT90840 will assert an automatic correction, and set the RXPAA interrupt bit
high. The serial port data and the ST bus frame pulse (F0o) will jump phase due to this correction, causing one
errored TDM frame. The PPCE bit indicates a change in framing at the receive parallel port which may cause a
“cascade” correction at SPCKo.
If a CPU write to the Receive Path Connection Memory is occurring during the one 4.096 MHz clock cycle that
clocks the correction, there is a chance that the write data will go to Stream0-Channel0, or Stream1-Channel0,
rather than the intended address. To avoid this it is necessary to keep clocks stable during RPCM programming in
TM2 (including not using DIN while programming). If there is some doubt about the quality of the clocks in a
particular application, options include:
-1- Program RPCM in TM1, where this correction does not occur.
-2- Program RPCM in TM2 with Internal Clock mode, (INTCLK=1) where this correction does not occur.
-3- Monitor the RXPAA interrupt bit during RPCM programming, and check the ST0-Ch0 and ST1-Ch0 addresses if
an alarm occurs.
-4- Read/verify ST0-Ch0 and ST1-Ch0 after a block of RPCM writes. If either is corrupted, one of the writes
occurred during a clock correction.
Memory Block-Programming
The MT90840 allows the user to program one value into the entire Transmit Path Connect Memory High, or
Receive Path Connect Memory High, with a single register write. This feature allows the four most significant bits of
each byte in the TPCM High, or RPCM High, to be automatically programmed with the value of the 4 PBD bits of
the GPM register. This eases system initialization by allowing all channels to be placed in high-impedance, or all
channels to be placed in bypass. The procedure works as follows:
a) The SEL2-0 bits in the Control Register are used to select Block-Programming for either the TPCM High, or
b) The GPM Register is written. The CPU sets the Block-Programming Enable (BPE) bit to HIGH and the
c) The user waits 250 µsec (two frames) to allow the TPCM High (2430 positions) or RPCM High (512
d) After 250 µsec, the user should check that the BPE bit is LOW, indicating that the Block Program completed
Procedures a, b, c, and d must be performed twice if both TPCM and RPCM have to be initialized.
Block-programming requires stable F0 and PPFRi framing to function properly. If the framing jumps during block-
programming, a section of memory may be missed. RPCM block-programming is dependent on the C4/8 serial port
clock and F0 framing. TPCM block programming is dependent on the PCKT clock, and F0 framing (PCKR, PPFRi
and F0 in TM2). DIN should not be active during block programming.
If there is some doubt about the quality of the clocks in a particular application, block-programming options include:
-1- If a stable C4/8 serial port clock is not available, or if a stable F0i frame is not available, use TM2 with Internal
Clocks (INTCLK=1) to perform block-programming of RPCM.
-2- If stable PPFRi framing is not available in TM2, disable the external gate driving PPFRi and use free-running
framing to perform block-programming of TPCM (and/or Internal Clocks mode to block-program RPCM).
the RPCM High blocks. It is also necessary to select the serial port mode (with DR1-0 and FDC in the IMS
register) before programming the RPCM.
Block-Programming Data (BPD7-4) bits to the desired value. This action causes the contents of the BPD7-
4 bits to be loaded into the four most significant bits of all addresses in TPCM High, or RPCM High (as set
by the Control Register).
positions) to be entirely loaded with the new pattern.
successfully. If the BPE bit does not return to LOW, the necessary TDM clock input may not be available.
The BPE bit can be written LOW to force an end to the Block Programming.
Zarlink Semiconductor Inc.
MT90840
30
Data Sheet