MT90840AP Zarlink, MT90840AP Datasheet - Page 21

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Naming rules:
ELD:
P/S:
Pi:
Po:
S/P:
Si:
So:
Transmission: The delay due to electronic circuits and physical media connecting the parallel ports of two MT90840s. (Assumed to be negligible in
TM3.)
Note 1: Exact P/S or S/P delay depends on relative positions of PPFRi and F0 +/- 120 nsec tolerance).
Note 2: Actual TM1 P/S and P/P delay depends on elastic position of PPFRi with respect to F0i (see ELD definition).
Note 3: Bypass delay in TM2: PPFT and PDo ch.0 are co-incident with PDi ch.235 at 19.44 MHz, ch.199 at 16 MHz, and ch.80 at 6.48 MHz. (TCP
= 1 delays PDo ch.0 an extra half clock-cycle in TM2).
Note 4: “Round-trip” delay from/to serial ports with the same F0 is always an integral number of frames (plus switching: So - Si).
Per-channel Control Outputs on the Parallel Port
The MT90840 provides four control outputs (CTo0-CTo3) which are synchronized to the parallel port output timing.
Each of the CTo output pins is controlled by the CT0-3 bits of the TPCM High. (The CTo0 pin and bit are
programmed with the Output Enable data.) The contents of the CTo bit in each TPCM High location is output on the
corresponding CTo pin once every frame. See Figure 9. The control outputs can be used to control other devices,
such as buffers, to allow sharing of the parallel port data bus.
Per-channel Tri-state (Serial and Parallel)
The MT90840 provides per-channel tri-state of the output pins on both the serial and parallel port. The OE bit in
each address of the TPCM and RPCM determines if data will be driven during a particular time slot, or if the pin will
be placed in a high-impedance state during that time slot. The OE bit overrides all other per-channel control bits.
Per-channel Message Mode (Serial and Parallel)
The MT90840 provides per-channel message mode capability on both the serial and parallel port. The MC bit in
each address of the TPCM and RPCM determines if the Connection Memory Low byte is to be used as an address,
or as data to be output on the particular channel (message mode). When the MC bit is HIGH, the Connection
Memory Low byte is used as message data. As well as driving message data on the serial (RPCM) and parallel
(TPCM) ports, the MT90840 allows the CPU to read serial or parallel data channels from the TPDM or RPDM.
Applications for message mode include digital silence, proprietary signalling, and creating fixed 8 kHz framing
patterns.
TM1 S/P +
TM2 P/S +
TM2 S/P +
TM1 P/S
TM1 S/P +
TM2 Bypass
+ TM1 P/S
TM3 S/P +
TM3 P/S
Mode
ELastic Delay, measured from PPFRi to F0i (4.4 to 129.4 µsec).
Parallel-to-Serial data path.
Parallel Input channel time, expressed in delay after PPFRi (0 to 125 µsec).
Parallel Output channel time, expressed in delay after PPFTi/o (0 to 125 µsec).
Serial-to-Parallel data path.
Serial Input channel time, expressed in delay after F0i/o (0 to 125 µsec).
Serial Output channel time, expressed in delay after F0i/o (0 to 125 µsec).
All
All
All
Data Rates
Table 1 - MT90840 Throughput Delay Summary
Dmin = 4 frames
= 500
Dmin = 2 frames
= 250
Dmin = 250
Minimum Delay
µ
µ
sec
sec
Zarlink Semiconductor Inc.
µ
sec
MT90840
21
D = (2 X 12)
So - Si = {5 or more integral frames} + So - Si
(Note 4)
D = (3 X 12)
So - Si
= {3 or more integral frames} + So - Si
(Note 4)
D = (7.7 + 117.3)
= 375
Min. 250
µ
sec + So - Si
µ
sec, Avg. 375
µ
µ
sec + 4 frames + 2 X Transmission + ELD +
sec + 2 frames + 2 X Transmission + ELD +
Total Throughput Delay
µ
sec + 2 frames + So - Si
µ
sec, Max. 500
µ
sec (Note 4)
Data Sheet