MT90840AP Zarlink, MT90840AP Datasheet - Page 11

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

MT90840
Data Sheet
Transmit Path Data Memory
The Tx Path Data Memory is structured as 512 words of 8 bits. Serial input time slots are converted to parallel bytes
and copied to the Tx Path Data Memory sequentially, serial-stream by serial-stream. The lowest address of the Tx
Path Data Memory is STi0-channel0, the next is STi0-channel1, and so on. At 2 Mbps, with 32 channels per STi pin,
STi1-channel0 would be 32 addresses higher than STi0-channel0. The Tx Path Data Memory is read out to the
parallel outputs by the Tx Connection Memory.
Receive Path
The Receive Path is from the parallel inputs (PDi0-7), through the Receive (Rx) Path Data Memory, to the serial
outputs. This path is controlled by the contents of the Rx Path Connection Memory. The Rx Path Connection
Memory is programmed, for each output time slot, with the address-value of the source channel to be read out of
the Rx Path Data Memory. Up to 2430 channels of parallel input can be switched to up to 512 channels of serial
output. Each output byte, whether switched data or message mode data, is read from memory and passed to the
parallel-to-serial converters, and then driven out the serial port.
Receive Path Connection Memory
The Rx Path Connection Memory is structured as 512 words of 16 bits. This supports up to 512 DS0 channels. The
Rx Path Connection Memory is accessed as two sub-memories: High and Low. The Connection Memory Low (512
x 8) is the low byte of the word, and is programmed with the address-value of the parallel-input source channel. The
Connection Memory High (512 x 8) is the high byte of the word. Connection Memory High holds the high-order bits
of the source address-value, and is also programmed to control per-channel functions such as output driver-enable
and direction-control.
Receive Path Data Memory
The Rx Path Data Memory is structured as 2430 words of 8 bits (1 byte). Parallel input time slots are copied to the
Rx Path Data Memory sequentially. The Rx Path Data Memory is read out to the serial port by the Rx Path
Connection Memory.
Bypass/Parallel-Switching Path
The Bypass/Parallel Switching path is from parallel input to parallel output. Data received at the parallel inputs
(PDi0-7) is copied to the Rx Path Receive Memory, and may be passed to the parallel outputs (PDo0-7) under
control of the Tx Path Connection Memory.
Bypass
In ring timing modes (TM1 and TM2) this is a bypass path. When the Bypass bit (PPBY) for a given parallel output
channel is set in the Tx Path Connection Memory, the same-address parallel input channel is copied (bypassed) to
that parallel output channel. This allows data channels not destined for the local node to be bypassed to the output
port and down the ring. “Broadcast” channels destined for every node can also be bypassed, since PPBY is an
output control, and it does not affect the availability of the Receive Parallel data for switching to the serial port or
monitoring through the CPU interface.
Parallel Switching
In Parallel Switching Mode (TM4) this is a switching path, and the Tx Path Connection Memory is programmed to
switch parallel inputs to parallel outputs. For each parallel output channel control-address, the Tx Path Connection
Memory is programmed with the 12-bit address-value of the desired parallel input channel.
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Zarlink Semiconductor Inc.