DS90C387VJDX National Semiconductor, DS90C387VJDX Datasheet - Page 14

• Manufacturer Part Number: DS90C387VJDX
• Description: LVDS Flat Panel Display 0.45V 100-Pin TQFP T/R
• Manufacturer: National Semiconductor

Specifications of DS90C387VJDX

• Package: 100TQFP
• Number Of Elements Per Chip: 8
• Transmission Data Rate: 5380 Mbps
• Differential Input Low Threshold Voltage: -0.1 V
• Differential Input High Threshold Voltage: 0.1 V
• Typical Operating Supply Voltage: 3.3 V

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DS90CF388 Pin Descriptions — FPD Link Receiver
Note 15: The DS90CF388 is designed to automatically detect the DC Balance or non-DC Balance transmitted data from the DS90C387 and deserialize the LVDS
data according to the defined bit mapping.
AnP
AnM
Rn, Gn, Bn,
DE, HSYNC,
VSYNC
RxCLK INP
RxCLK INM
RxCLK OUT
R_FDE
PLLSEL
BAL
DESKEW
PD
STOPCLK
V
GND
PLLV
PLLGND
LVDSV
LVDSGND
CNTLE,
CNTLF
CC
Pin Name
FIGURE 16. Resistor Network for “DUAL” pin input - recommend using R1=R2=10kΩ for single to dual mode
CC
CC
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
No.
51
8
8
1
1
1
1
1
1
1
1
1
6
8
1
2
2
3
2
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 16 Red, 16 Green, 16 Blue, and 3
control lines — HSYNC (LP), VSYNC (FLM), DE (Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL level clock output. The falling edge acts as data strobe.
Programmable control (DE) strobe select. Tied high for data active when DE
is high. (Note 12)
PLL range select. This pin must be tied to V
Ground is reserved for future use. Typical shift point is between 55 and 68
MHz. (Notes 13, 14)
Mode select for DC Balanced (new) or non-DC Balanced (backward
compatible) interface. BAL = LOW for non-DC Balanced mode. BAL = HIGH
for DC Balanced Mode (Auto-detect mode), with this pin HIGH the received
LVDS clock signal is used to determine if the interface is in new or backward
compatible mode. (Notes 12, 13, 15)
Deskew and oversampling “on/off” select. Deskew is active when input is
high. Only supported in DC Balance mode (BAL=High). To complete the
deskew operation, a minimum of four clock cycles is required during
blanking time. (Note 12)
TTL level input. When asserted (low input) the receiver data outputs are low
and clock output is high. (Note 12)
Indicates receiver clock input signal is not present with a logic high. With a
clock input present, a low logic is indicated.
Power supply pins for TTL outputs and digital circuitry.
Ground pins for TTL outputs and digital circuitry
Power supply for PLL circuitry.
Ground pin for PLL circuitry.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
TTL level data outputs. User-defined control signals - no connect when not
used.
14
10007308
Description
CC
for auto-range. NC or tied to