DS90C387VJDX National Semiconductor, DS90C387VJDX Datasheet - Page 11

• Manufacturer Part Number: DS90C387VJDX
• Description: LVDS Flat Panel Display 0.45V 100-Pin TQFP T/R
• Manufacturer: National Semiconductor

Specifications of DS90C387VJDX

• Package: 100TQFP
• Number Of Elements Per Chip: 8
• Transmission Data Rate: 5380 Mbps
• Differential Input Low Threshold Voltage: -0.1 V
• Differential Input High Threshold Voltage: 0.1 V
• Typical Operating Supply Voltage: 3.3 V

AC Timing Diagrams
C — Setup and Hold Time (Internal data sampling window) defined by RSPOS (receiver input strobe position) min and max
TPPOS — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
See Applications Informations section for more details.
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
RSKMD ≥ TPPOSvariance (d) + TJCC (output jitter)(f) + ISI (m)
See Applications Informations section for more details.
j
j
j
j
j
j
Cable Skew — typically 10 ps to 40 ps per foot, media dependent
TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
ISI is dependent on interconnect length; may be zero
d = Tppos — Transmitter output pulse position (min and max)
f = TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
m = extra margin - assigned to ISI in long cable applications
FIGURE 13. Receiver Skew Margin (RSKMD) with DESKEW
(Continued)
FIGURE 12. Receiver Skew Margin
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