CX28229G-14 Mindspeed Technologies, CX28229G-14 Datasheet - Page 78

• Manufacturer Part Number: CX28229G-14
• Description: ATM IMA 800Mbps 1.8V/3.3V 256-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CX28229G-14

• Package: 256BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3 V
• Maximum Operating Supply Voltage: 1.89|3.6 V
• Maximum Output Rate: 800 Mbps

UTOPIA Interfaces
4.1
4.2
4-2
General UTOPIA Operation
UTOPIA 8-bit and 16-bit Bus Widths
Three primary functions are performed by the UTOPIA controller: polling, selection,
and data transfer. These functions are basically the same for both the transmit and
receive sides of the UTOPIA bus. The following example describes the transmit
functions. Refer to
The ATM layer UTOPIA controller polls the connected PHY ports by transmitting
the port addresses on the UTxAddr lines. If a port is ready to transfer data, it asserts
UTxClAv. Note that the process of polling a port does NOT result in that port being
selected to transfer data! Polling allows the controller to determine which port is
ready for data; it must then select that port before sending data. It does so by
reasserting the desired address and then asserting UtxEnb*. The PHY will then be
ready to transfer data on the UTxData lines. UTxEnb* is deasserted when the transfer
is completed. Polling can continue during the data transfer process but not during port
selection. It operates independently of the state of UTxEnb*.
To pause the data transfer, UTxEnb* can be deasserted. To continue the transfer, the
controller must reselect the port by transmitting its address one clock cycle before
asserting UTxEnb*. The controller must ensure that the cell transfer from this port has
been completed, to avoid a start-of-cell error.
The CX2822x has two bus width options, 8-bit or 16-bit, which are selected in
BusWidth, bit 2, of the MODE register (0x0202). The protocols and timing are the
same in both modes, except that 8-bit mode uses only the lower half of the data bus
(TxData[7:0] and RxData[7:0]) and parity is only generated or checked over those
bits. UTOPIA Level 2 8-bit operates up to 33 MHz and Level 2 16-bit up to 50MHz.
In 8-bit mode, each ATM cell consists of 53 bytes. The first five bytes are used for
header information. The remaining bytes are used for payload.
In 16-bit mode, the cell consists of 54 bytes. The first five bytes contain header
information. The sixth byte, UDF2, is required to maintain alignment but is not read
by the CX2822x. The remaining bytes are used for payload.
NOTE:
CX28224 only supports 8 bit UTOPIA.
Mindspeed Technologies
Figure
4-1.
™
CX28224/5/9 Data Sheet
28229-DSH-001-D