XCV600E-6BGG432C Xilinx Inc, XCV600E-6BGG432C Datasheet - Page 15

• Manufacturer Part Number: XCV600E-6BGG432C
• Description: FPGA Virtex-E Family 186.624K Gates 15552 Cells 357MHz 0.18um (CMOS) Technology 1.8V 432-Pin BGA
• Manufacturer: Xilinx Inc

Specifications of XCV600E-6BGG432C

• Package: 432BGA
• Family Name: Virtex-E
• Device Logic Gates: 186624
• Device Logic Units: 15552
• Device System Gates: 985882
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 316
• Ram Bits: 294912
• Re-programmability Support: Yes

Instruction Set
The Virtex-E series Boundary Scan instruction set also
includes instructions to configure the device and read back
configuration data (CFG_IN, CFG_OUT, and JSTART). The
complete instruction set is coded as shown in
Table 6: Boundary Scan Instructions
DS022-2 (v2.8) January 16, 2006
Production Product Specification
EXTEST
SAMPLE/
PRELOAD
USER1
USER2
CFG_OUT
Boundary Scan
Command
R
TDI
Code(4:0)
IOB
IOB
IOB
IOB
IOB
IOB
IOB
Binary
00000
00001
00010
00011
00100
IOB
INSTRUCTION REGISTER
IOB
REGISTER
Enables Boundary Scan
EXTEST operation
Enables Boundary Scan
SAMPLE/PRELOAD
operation
Access user-defined
register 1
Access user-defined
register 2
Access the
configuration bus for
read operations.
BYPASS
IOB
Figure 11: Virtex-E Family Boundary Scan Logic
IOB
Description
IOB
Table
IOB
IOB
IOB
IOB
IOB
IOB
IOB
M
U
X
TDO
6..
www.xilinx.com
IOB.Q
IOB.T
IOB.T
IOB.I
IOB.I
CAPTURE
SHIFT/
Table 6: Boundary Scan Instructions (Continued)
DATAOUT
CFG_IN
INTEST
USERCODE
IDCODE
HIGHZ
JSTART
BYPASS
RESERVED
Boundary Scan
DATA IN
Command
CLOCK DATA
1
0
1
0
1
0
1
0
1
0
REGISTER
Virtex™-E 1.8 V Field Programmable Gate Arrays
D
D
D
D
D
Q
Q
Q
Q
Q
UPDATE
D
D
D
D
D
LE
LE
LE
LE
LE
Code(4:0)
All other
sd
sd
sd
sd
sd
Binary
00101
00111
01000
01001
01010
01100
11111
codes
Q
Q
Q
Q
Q
0
1
1
0
1
0
0
1
1
0
EXTEST
Access the
configuration bus for
write operations.
Enables Boundary Scan
INTEST operation
Enables shifting out
USER code
Enables shifting out of
ID Code
3-states output pins
while enabling the
Bypass Register
Clock the start-up
sequence when
StartupClk is TCK
Enables BYPASS
Xilinx reserved
instructions
X9016
Description
Module 2 of 4
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