MACH211-15VC Lattice, MACH211-15VC Datasheet - Page 37

• Manufacturer Part Number: MACH211-15VC
• Description: CPLD MACH 2 Family 2.5K Gates 64 Macro Cells 66.6MHz EECMOS Technology 5V 44-Pin TQFP
• Manufacturer: Lattice

Specifications of MACH211-15VC

• Package: 44TQFP
• Family Name: MACH 2
• Device System Gates: 2500
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.6 MHz
• Number Of Product Terms Per Macro: 16
• Operating Temperature: 0 to 70 °C

84-PIN PLCC CONNECTION DIAGRAM (MACH131-5/7/10/12/15)
Top View
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
I/O
V
CC
= Input
= Input/Output
= Supply Voltage
CLK0/I0
CLK1/I1
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O22
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O23
GND
GND
VCC
I/O8
I/O9
Block B
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
11
33
Block A
10
34
35
9
36
8
37
7
38
6
39
5
MACH 1 & 2 Families
40
4
41
84-Pin PLCC
3
42
2
43
1
84
44
83
45
82
46
81
47
80
48
79
49
78
50
Block C
Block D
77
51
76
52
75
53
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
GND
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
CLK3/I4
GND
VCC
CLK2/I3
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
14051K-020
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