XC3S500E-4FG320C Xilinx Inc, XC3S500E-4FG320C Datasheet - Page 19

• Manufacturer Part Number: XC3S500E-4FG320C
• Description: FPGA Spartan-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 320-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC3S500E-4FG320C

• Package: 320FBGA
• Family Name: Spartan-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 232
• Ram Bits: 368640

Table 8: Programmable Output Drive Current
High output current drive strength and FAST output slew
rates generally result in fastest I/O performance. However,
these same settings generally also result in transmission
line effects on the printed circuit board (PCB) for all but the
shortest board traces. Each IOB has independent slew rate
and drive strength controls. Use the slowest slew rate and
lowest output drive current that meets the performance
requirements for the end application.
Likewise, due to lead inductance, a given package supports
a limited number of simultaneous switching outputs (SSOs)
when using fast, high-drive outputs. Only use fast,
high-drive outputs when required by the application.
IOBs Organized into Banks
The Spartan-3E architecture organizes IOBs into four I/O
banks as shown in
rate V
each bank to independently set V
supplies can be set for each bank. Refer to
Table 7
When working with Spartan-3E devices, most of the differ-
ential I/O standards are compatible and can be combined
within any given bank. Each bank can support any two of
the following differential standards: LVDS_25 outputs,
MINI_LVDS_25 outputs, and RSDS_25 outputs. As an
example, LVDS_25 outputs, RSDS_25 outputs, and any
other differential inputs while using on-chip differential ter-
mination are a valid combination. A combination not allowed
is a single bank with LVDS_25 outputs, RSDS_25 outputs,
and MINI_LVDS_25 outputs.
DS312-2 (v3.8) August 26, 2009
Product Specification
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
IOSTANDARD
CCO
Figure 13: Spartan-3E I/O Banks (top view)
for V
and V
R
CCO
REF
and V
2
Figure
supplies. The separate supplies allow
REF
Output Drive Current (mA)
Bank 0
Bank 2
4
-
13. Each bank maintains sepa-
requirements.
DS312-2_26_021205
6
-
CCO
. Similarly, the V
8
-
-
Table 6
12
-
-
-
www.xilinx.com
16
-
-
-
-
and
REF
I/O Banking Rules
When assigning I/Os to banks, these V
followed:
1. All V
2. All V
3. The V
4. If a bank does not have any V
If any of the standards assigned to the Inputs of the bank
use V
observed:
1. All V
2. All V
3. The V
If V
all associated V
user I/Os or input pins.
Package Footprint Compatibility
Sometimes, applications outgrow the logic capacity of a
specific Spartan-3E FPGA. Fortunately, the Spartan-3E
family is designed so that multiple part types are available in
pin-compatible package footprints, as described in
Descriptions
differences between devices available in the same footprint.
These differences are outlined for each package, such as
pins that are unconnected on one device but connected on
another in the same package or pins that are dedicated
inputs on one package but full I/O on another. When design-
ing the printed circuit board (PCB), plan for potential future
upgrades and package migration.
The Spartan-3E family is not pin-compatible with any previ-
ous Xilinx FPGA family.
Dedicated Inputs
Dedicated Inputs are IOBs used only as inputs. Pin names
designate a Dedicated Input if the name starts with IP, for
example, IP or IP_Lxxx_x. Dedicated inputs retain the full
functionality of the IOB for input functions with a single
REF
bank is unused.
the same voltage level.
I/Os of any given bank must agree. The Xilinx
development software checks for this.
Table 7
supply.
connect V
3.3V. Some configuration modes might place additional
V
information.
the same voltage level.
Inputs of the bank must agree. The Xilinx development
software checks for this.
standards use the V
CCO
REF
is not required to bias the input switching thresholds,
CCO
CCO
REF
REF
, then the following additional rules must be
CCO
REF
requirements. Refer to
describe how different standards use the V
pins must be connected within a bank.
lines associated with the bank must be set to
pins on the FPGA must be connected even if a
lines associated within a bank must be set to
CCO
levels used by all standards assigned to the
in Module 4. In some cases, there are subtle
levels used by all standards assigned to the
REF
to an available voltage, such as 2.5V or
pins within the bank can be used as
REF
Table 6
supply.
Configuration
CCO
Functional Description
describes how different
requirements,
CCO
Table 6
rules must be
for more
and
Pinout
CCO
19