PC82573E Intel, PC82573E Datasheet - Page 21

• Manufacturer Part Number: PC82573E
• Description: Ethernet CTLR Single Chip 10Mbps/100Mbps/1000Mbps 1.2V/2.5V/3.3V 196-Pin TFBGA
• Manufacturer: Intel

Specifications of PC82573E

• Package: 196TFBGA
• Standard Supported: IEEE 1149.1|IEEE 802.3|IEEE 802.3ab|IEEE 802.3q1|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Data Rate: 10|100|1000 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 1.2|2.5|3.3 V
• Dma Support: Yes
• Maximum Power Dissipation: 1.35 W

Datasheet—82573
3.3.4
3.3.4.1
Figure 3.
3.3.4.2
Power Up Sequencing and Tracking
Power Supply Sequencing
Internal LVR Power Down Sequencing
Internal LVR Power Sequencing
All supplies should rise monotonically. Sequencing of the supplies is controlled by the
82573.
During power up, the sequencing and tracking of the internally controlled supplies
(2.5V and 1.2V) are controlled by the 82573. No specific motherboard requirements
are necessary to prevent electrical overstress or latch-up.
The 82573 analog voltage (2.5V) never exceeds the 3.3V supply at any time during the
power up. This is because the 2.5V supply is generated from the 3.3V supply when the
internal voltage regulator control logic is being used.
circuit. The 2.5V supply tracks the 3.3V ramp.
The 82573 core voltage (1.2V) never exceeds the 3.3V at any time during the power
up. This is because the 2.5V supply is generated from the 3.3V supply when the
internal voltage regulator control logic is being used.
circuit. The 1.2V ramp is delayed internally to prevent it from exceeding the 2.5V and
3.3V supply at any time. The delay is proportional to the slope of the 3.3V ramp.
The delay is approximated by T
T
circuit.
There are no specific power down sequencing and tracking requirements for the 82573
device. The risk of latch-up or electrical overstress is small because the only charge
storing in decoupling capacitors is left in the system.
Voltage
ramp
• It is recommended that the voltage on a lower voltage rail never exceed the
• There are no minimum time requirements between the voltage rails as long as they
• All 3 supplies must be stable for at least 80 ms before LAN_PWR_GOOD is
• A PCIe* reset must occur after LAN Power Good is active.
voltage on a higher voltage rail during power on.
power up in sequence: 3.3V → 2.5V → 1.2V.
asserted. 100 ms is preferable if possible.
is defined to the ramp rate of the 3.3V input to the internal voltage regulator
0
3.3V
2.5V
ramp
(3.3V)*0.25 < T
Minimum 80 ms
1.2V
delay
Figure 3
Figure 3
(1.2V) < T
shows the internal LVR
shows the internal LVR
ramp
LAN_PWR_GOOD
(3.3V)*0.75.
Time
21