MACH445-15YC Lattice, MACH445-15YC Datasheet - Page 11

• Manufacturer Part Number: MACH445-15YC
• Description: CPLD MACH 4 Family 128 Macro Cells 47.6MHz EECMOS Technology 5V 100-Pin PQFP Tray
• Manufacturer: Lattice

Specifications of MACH445-15YC

• Package: 100PQFP
• Family Name: MACH 4
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 47.6 MHz
• Number Of Product Terms Per Macro: 20
• Memory Type: EEPROM
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
(continued)
Input Register with Standard-Hold-Time Option
Parameter
Symbol
f
t
t
t
t
t
t
t
MAXIR
t
t
t
t
t
t
WICH
t
t
t
WICL
WIGL
t
t
PDLL
IGOL
IGSA
IGSS
ARW
t
t
SLLA
SLLS
t
ARR
t
APW
t
t
APR
PDL
IGO
HIR
ICS
SIR
HIL
AR
AP
EA
ER
SIL
Parameter Description
Input Register Clock to Output Register Setup
Maximum Input Register Frequency
Input Latch Gate to Combinatorial Output
Input Latch Gate to Output Through Transparent
Output Latch
Input Latch Gate to Output Latch Setup Using
Product Term Output Latch Gate
Input Latch Gate to Output Latch Setup Using Global
Output Latch Gate
Input Latch Gate Width LOW
Asynchronous Reset to Registered or Latched Output
Asynchronous Reset Width (Note 2)
Asynchronous Reset Recovery Time (Note 2)
Asynchronous Preset to Registered or Latched Output
Asynchronous Preset Width (Note 2)
Asynchronous Preset Recovery Time (Note 2)
Input, I/O, or Feedback to Output Enable
Input, I/O, or Feedback to Output Disable
Input, I/O, or Feedback to Output Through
Transparent Input Latch
Input Register Setup Time
Input Register Hold Time
Input Latch Setup Time
Input Latch Hold Time
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Product Term Output
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Gate
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
Input Register Clock Width
MACH445-12 (Com’l)
1/(t
WICL
+ t
Gate
WICH
)
D-type
T-type
LOW
HIGH
83.3
Min
10
12
10
12
6
6
9
4
9
6
8
2
2
2
3
2
3
4
9
-12
Max
16
18
16
16
12
12
14
16
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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