MACH445 Lattice Semiconductor Corp., MACH445 Datasheet
MACH445
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MACH445 Summary of contents
Page 1
... The input switch matrix provides input signals with alternative paths into the central switch matrix; the output switch matrix provides flexibility in assigning macrocells to I/O pins. The MACH445 has macrocells that can be configured as synchronous or asynchronous. This allows designers to implement both synchronous and Lattice Semiconductor ...
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... Clock Generator 2 I2, I5 Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4 MACH445-12/15/20 OE Clock Generator OE Clock Generator OE Clock Generator OE Clock Generator 17468E-1 ...
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... CONNECTION DIAGRAM MACH445 (MACH435) Top View 1 GND GND 2 TDI I/ I/O9 7 I/O10 8 I/O11 I/O12 9 10 I/O13 11 I/O14 I/O15 12 I0/CLK0 13 14 VCC VCC 15 16 GND 17 GND I1/CLK1 18 19 I/O16 20 I/O17 I/O18 21 22 I/O19 I/O20 23 I/O21 24 I/O22 25 I/O23 26 27 TMS 28 TCK 29 GND ...
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... The Valid Combinations table lists configurations planned to be supported in volume for this device. Con- YC sult your local sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. MACH445-12/15/20 OPTIONAL PROCESSING Blank = Shipped in Trays OPERATING CONDITIONS C = Commercial ( +70 C) PACKAGE TYPE ...
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... PAL block. The Logic Allocator The logic allocator in the MACH445 takes the 80 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven product terms in synchronous mode product terms in asynchronous mode ...
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... The I/O Cell The I/O cell in the MACH445 consists of a three-state buffer and an input flip-flop. The I/O cell is driven by one of the macrocells, as selected by the output switch matrix. Each I/O cell can take its input from one of eight macrocells ...
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... Test Access Port. Use of the programming Enable Pin (ENABLE*) is optional. Zero-Hold-Time Input Register The MACH445 device has a zero-hold time (ZHT) fuse. This fuse controls the time delay associated with loading data into all I/O cell registers and latches in the MACH445 device ...
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... Macrocell M6 C7 Macrocell M7 C8 Macrocell M8 C9 Macrocell M9 C10 Macrocell M10 C11 M11 Macrocell C12 Macrocell M12 C13 Macrocell M13 C14 Macrocell M14 C15 Macrocell M15 16 16 Figure 1. MACH445 PAL Block MACH445-12/15/ I/O0 I/O Cell I/O I/O1 Cell I/O I/O2 Cell I/O3 I/O Cell I/O I/O4 Cell ...
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... 5 =25 MHz Test Conditions MHz OUT and I (or I and OZL IH OZH MACH445-12 (Com’l) ) Operating + with +4. +5.25 V Min Typ = Min 2.4 2.0 – mA) 255 OUT = 25 C (Note 5) A Typ = 5 ...
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... Global Gate Width LOW (for LOW transparent) GWS or HIGH (for HIGH transparent) t Input Register Clock to Combinatorial Output ICO 10 External Feedback Internal Feedback (f ) CNTA No Feedback (Note 3) External Feedback Internal Feedback (f ) CNTS No Feedback (Note 3) MACH445-12 (Com’l) -12 Min Max Unit D-type 5 ns T-type ...
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... Transparent Input Latch to Product Term Output t Setup Time from Input, I/O, or Feedback Through SLLS Transparent Input Latch to Output Gate t Input, I/O, or Feedback to Output Through Transparent PDLL Input and Output Latches 1/( WICL WICH Gate MACH445-12 (Com’l) -12 Min Max Unit D-type 9 ns T-type 10 ns LOW 6 ns HIGH ...
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... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 12 Gate MACH445-12 (Com’l) -12 Min Max Unit ...
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... OUT CC f =25 MHz (Note 5) A Test Conditions MHz OUT and I (or I and OZL IH OZH MACH445-15/20 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 255 Typ = 25 C, ...
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... WHA D-type 10 T-type LOW 6 HIGH 6 D-type COS T-type 47.6 D-type 66.6 ) CNTS T-type 62.5 1/( WLS WHS 83 MACH445-15/20 (Com’l) -20 Max Min Max Unit 31.2 MHz 30.3 MHz 37 MHz 35.7 MHz 41.7 MHz ...
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... Input and Output Latches -15 Min D-type 15 T-type 16 LOW 6 HIGH 6 1/( 83.3 WICL WICH Disable (Note Gate 12 MACH445-15/20 (Com’l) -20 Max Min Max Unit 62.5 MHz ...
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... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 16 -15 Min Gate 18 MACH445-15/20 (Com’l) -20 Max Min Max Unit ...
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... Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACH445-12/15/ 1.0 17468E (V) OH 17468E 17468E-6 17 ...
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... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register Frequency (MHz) MACH445-12/15/20 MACH445 17468E-7 ...
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... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air MACH445-12/15/20 Typ PQFP Unit 5 C/W ...
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... Gate t WL 17468E- Registered Input t HIR Input V T Register Clock t ICO V T Output Register Clock 17468E-13 MACH445-12/15/ 17468E PDL Latched Output (MACH 2, 3, and GWS Gate Width (MACH 2, 3, and ICS ...
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... Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL Latched Input (MACH 2 and 4) t IGOL Latched Input and Output (MACH 2, 3, and 4) MACH445-12/15/ IGO V T 17468E-15 t PDLL SLL ...
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... Gate t WICL 17468E-17 Input, I/ Feedback Registered V T Output t ARR Clock V T 17468E- Outputs + V OL Output Disable/Enable MACH445-12/15/20 t WIGL Input Latch Gate Width (MACH 2 and 4) t APW Asynchronous Preset 0. 0.5V 17468E- 17468E- APR ...
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... Apply Output Commercial 300 390 5 pF MACH445-12/15/20 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL Test Point 17468E-22 Measured ...
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... All frequencies except f MAX other measured AC parameters. f ured directly. ” (SECOND CHIP MACH445-12/15/ type is the mini- MAX + t ). Usually, this minimum feedback.” MAX . Because this involves no MAXIR + the sum of SIR HIR + t ). The clock widths are nor- ...
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... Min Pattern Data Retention Time Max Reprogramming Cycles bipolar parts result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Min Units 10 Years 20 Years 100 Cycles MACH445-12/15/20 Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions 25 ...
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... INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection Input 100 k Preload Feedback Circuitry Input I/O MACH445-12/15/20 CC 100 17468E-24 ...
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... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACH445-12/15/20 can rise to its steady state, two CC rise must be monotonic. Max 10 See Switching Characteristics V CC ...
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... All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support Preload Off Mode Figure 2. Preload/Reset Conflict Set Reset Figure 3. Combinatorial Latch MACH445-12/15/20 Preloaded HIGH Preloaded HIGH 17468E-26 17468E-27 ...