72841L25TF Integrated Device Technology (Idt), 72841L25TF Datasheet - Page 7

• Manufacturer Part Number: 72841L25TF
• Description: FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin STQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72841L25TF

• Package: 64STQFP
• Configuration: Quad
• Bus Directional: Bi-Directional
• Density: 72 Kb
• Organization: 4Kx9x2
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTE:
1. For the purposes of this table, WENA1 and WENB1 = V
2. The same selection sequence applies to reading from the registers. RENA1 and
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
8
8
8
8
8
8
8
8
LDA
LDA
LDA
LDA
LDA WENA1
LDB
LDB
LDB
LDB
LDB
RENA2 (RENB1 and RENB2) are enabled and read is performed on the LOW-to-
HIGH transition of RCLKA (RCLKB).
0
0
1
1
Figure 2. Writing to Offset Registers for FIFOs A and B
7
7
WENA1
WENA1
WENA1
WENA1
WENB1
WENB1
WENB1
WENB1
WENB1
7
7
0
1
0
1
72801 - DUAL 256 x 9
72831 - DUAL 2,048 x 9
Empty Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB) Reg.
Default Value 007H
Empty Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB) Reg.
Default Value 007H
WCLKA
WCLKB
2
2
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
(MSB)
(MSB)
0
0
OPERATION ON FIFO B
OPERATION ON FIFO A
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
IH
.
7
7
7
7
72811 - DUAL 512 x 9
72841 - DUAL 4,096 x 9
Default Value 007H
Default Value 007H
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB)
Default Value 007H
Full Offset (LSB)
Full Offset (LSB)
TM
7
registers.
OUTPUTS:
operations, when Array A (B) is full. If no reads are performed after reset, FFA
(FFB) will go LOW after 256 writes to the IDT72801's FIFO A (B); 512 writes
to the IDT72811's FIFO A (B); 1,024 writes to the IDT72821's FIFO A (B); 2,048
writes to the IDT72831's FIFO A (B); 4,096 writes to the IDT72841's FIFO A
(B); or 8,192 writes to the IDT72851's FIFO A (B).
Write Clock WCLKA (WCLKB).
operations, when the read pointer is equal to the write pointer, indicating that
Array A (B) is empty.
the Read Clock RCLKA (RCLKB).
A read and write should not be performed simultaneously to the offset
Full Flag (FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write
FFA (FFB) is synchronized with respect to the LOW-to-HIGH transition of the
Empty Flag (EFA, EFB) — EFA (EFB) will go LOW, inhibiting further read
EFA (EFB) is synchronized with respect to the LOW-to-HIGH transition of
3
3
(MSB)
(MSB)
0
0
1
1
(MSB)
(MSB)
0
0
0
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
7
7
7
7
72821 - DUAL 1,024 x 9
72851 - DUAL 8,192 x 9
COMMERCIAL AND INDUSTRIAL
Full Offset (LSB) Reg.
Default Value 007H
Default Value 007H
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB)
Default Value 007H
Full Offset (LSB)
TEMPERATURE RANGES
4
4
JANUARY 13, 2009
(MSB)
(MSB)
1
1
0
0
3034 drw 04
(MSB)
(MSB)
0
0
0
0
0
0
0
0
0
0