72841L25TF Integrated Device Technology (Idt), 72841L25TF Datasheet - Page 3

• Manufacturer Part Number: 72841L25TF
• Description: FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin STQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72841L25TF

• Package: 64STQFP
• Configuration: Quad
• Bus Directional: Bi-Directional
• Density: 72 Kb
• Organization: 4Kx9x2
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

PIN DESCRIPTIONS
to as FIFO A and FIFO B, are identical in every respect. The following
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
DA0-DA8
DB0-DB8
RSA
WCLKA
WCLKB
WENA1
WENB1
WENA2/
WENB2/
QA0-QA8
QB0-QB8
RCLKA
RCLKB
RENA1
RENB1
RENA2
RENB2
OEA
OEB
EFA
EFB
PAEA
PAEB
PAFA
PAFB
FFA
FFB
VCC
GND
The IDT72801/72811/72821/72831/72841/72851s two FIFOs, referred
Symbol
,
RSB
LDA
LDB
A Data Inputs
B Data Inputs
Reset
Write Clock
Write Enable 1
Write Enable 2/
Load
A Data Outputs
B Data Outputs
Read Clock
Read Enable 1
Read Enable 2
Output Enable
Empty Flag
Programmable
Almost-Empty
Flag
Programmable
Almost-Full Flag
Full Flag
Power
Ground
Name
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
9-bit data inputs to RAM array A.
9-bit data inputs to RAM array B.
When
the first location;
LOW. After power-up, a reset of both FIFOs A and B is required before an initial Write.
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write
enable(s) are asserted.
If FIFO A (B) is configured to have programmable flags,
Enable pin that can be used. When
on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to have two write enables,
WENA1
will not be written into the FIFO if
FIFO A (B) is configured at reset to have either two write enables or programmable flags. If
is HIGH at reset, this pin operates as a second write enable. If WENA2/
at reset this pin operates as a control to load and read the programmable flag offsets for its respective array.
If the FIFO is configured to have two write enables,
and WENA2 (WENB2) must be HIGH to write data into FIFO A (B). Data will not be written into FIFO A (B)
if
LOW to write or read the programmable flag offsets.
9-bit data outputs from RAM array A.
9-bit data outputs from RAM array B.
Data is read from FIFO A (B) on a
(
When
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if
When
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the
When
outputs DA0-DA8 (DB0-DB8) will be in a high-impedance state.
When
When
When
appropriate offset register. The default offset at reset is Empty+7.
RCLKA (RCLKB).
When
offset register. The default offset at reset is Full-7.
When
When
+5V power supply pin.
0V ground pin.
RENB1
FFA
(
RSA
FFB
EFA
PAEA
PAFA
FFA
RENA1
RENA1
OEA
EFA
FFA
) and
(
WENB1
) is LOW. If the FIFO is configured to have programmable flags,
(
(
(
(
(
(
FFB
EFB
FFB
RSB
EFB
(
OEB
(
PAEB
PAFB
RENA2
(
(
RENB1
RENB1
) is LOW, FIFO A (B) is full and further data writes into the input are inhibited.
) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited.
) is HIGH, FIFO A (B) is not full.
) must be LOW and WENA2 (WENB2) must be HIGH to write data into the FIFO. Data
) is HIGH, FIFO A (B) is not empty.
) is set LOW, the associated internal read and write pointers of array A (B) are set to
) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If
) is LOW, FIFO A (B) is almost-full based on the offset programmed into the appropriate
) is LOW, FIFO A (B) is almost-empty based on the offset programmed into the
FFA
(
) and
) and
RENB2
(
FFB
RENA2
RENA2
TM
) and
) are asserted.
3
description defines the input and output signals for FIFO A. The correspond-
ing signal names for FIFO B are provided in parentheses.
FFA
PAFA
(
(
RENB2
RENB2
LOW
(
FFB
(
PAFB
-to-
) are LOW, data is read from FIFO A (B) on every
) are LOW, data is read from the FIFO A (B) on every
WENA1
) is LOW.
HIGH
) go HIGH, and
Description
FFA
(
WENB1
PAFA
transition of RCLKA (RCLKB) when
EFA
(
FFB
(
(
PAFB
) is synchronized to WCLKA (WCLKB).
EFB
) is LOW, data A (B) is written into the FIFO
) is synchronized to RCLKA (RCLKB).
PAEA
) is synchronized to WCLKA (WCLKB).
PAEA
(
PAEB
WENA1
WENA1
OEA
(
COMMERCIAL AND INDUSTRIAL
PAEB
) and
LDA
(
OEB
(
) is synchronized to
WENB1
(
LDA
EFA
WENB1
) is HIGH, the
TEMPERATURE RANGES
(WENB2/
JANUARY 13, 2009
(
EFB
) is the only Write
EFA
) must be LOW
(
RENA1
EFA
LDB
) go
(
EFB
) is held
(EFB) is LOW.
LDB
) is LOW.
) is LOW
LDA
(
LDB
)