MT90401AB1 Zarlink, MT90401AB1 Datasheet - Page 4

• Manufacturer Part Number: MT90401AB1
• Description: Framer SDH/SONET 3.3V 80-Pin LQFP EP Tray
• Manufacturer: Zarlink

Specifications of MT90401AB1

• Package: 80LQFP EP
• Number Of Transceivers: 1
• Standard Framing Format: SDH|SONET
• Maximum Supply Current: 150 mA
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V

Pin Description (continued)
Pin #
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PRIOOR
E3/DS3
C155N,
C155P
Name
VREF
C1.5o
V
V
V
V
SEC
Tms
V
FS2
FS1
Tdo
Tclk
Trst
PRI
Tdi
C6
IC
IC
SS2
SS3
DD2
SS4
DD
E3 or DS3 Selection (Input). In Hardware Mode a low on this pin selects a clock rate of
44.736 MHz for the C34/C44 pin, while a high selects a clock rate of 34.368 MHz. This pin
performs no function if the device is not in hardware mode.
Secondary Reference (Input).
(falling edge) used for synchronization. One of four possible frequencies ( 8kHz,
1.544 MHz, 2.048 MHz or 19.44 MHz) may be used. In hardware mode the selection of the
input reference is based upon the MS1, MS2 and RSEL control inputs.
Primary Reference (Input).
(falling edge) used for synchronization. One of four possible frequencies (8 kHz,
1.544 MHz, 2.048 MHz or 19.44 MHz) may be used. In hardware mode the selection of the
input reference is based upon the MS1, MS2 and RSEL control inputs.
Digital ground. 0 Volts
Internal Connection. Leave unconnected
Analog ground. 0 Volts
Positive Analog Power Supply. Analog supply.
Positive Power Supply. Digital supply.
LVDS 155.52 MHz (Output)). Differential outputs generating a 155.52 MHz clock
Digital ground. 0 Volts
LVDS Reference Voltage (Input).
IEEE 1149.1a Test Data Output (Output). If not used, this pin should be left unconnected.
IEEE 1149.1a Test Mode Selection (Input). If not used, this pin should be pulled high.
IEEE 1149.1a Test Clock Signal (Input). If not used, this pin should be pulled high.
IEEE 1149.1a Reset Signal (Input). If not used, this pin should be held low.
IEEE 1149.1a Test Data Input (Input). If not used, this pin should be pulled high.
Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four
possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI
and SEC inputs. For more details see FS2 bit description in Table 6 - Control Register 1
(Address 00H - Read/Write).
Frequency Select 1 (Input). This input, in conjunction with FS2, selects which of four
possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI
and SEC inputs. For more details see FS1 bit description in Table 6 - Control Register 1
(Address 00H - Read/Write).
Primary Reference Out Of Range (CMOS Output). A logic high at this pin indicates that
the primary reference is off the PLL center frequency by more than 12 ppm. The
measurement is done on a 1 second basis using a signal derived from the 20 MHz clock
input on C20i. When the accuracy of the 20 MHz clock is
range limits of the PRIOOR signal will be
Clock 1.544 MHz (CMOS Output). This output is used in T1 applications.
Clock 6.312 MHz (CMOS Output). This output is used for DS2 or J2 applications.
Internal Connection. Tie low for normal operation.
Zarlink Semiconductor Inc.
MT90401
This is one of two (PRI & SEC) input reference sources
4
This is one of two (PRI & SEC) input reference sources
Description
+
16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm.
±
4.6 ppm, the effective out of
Data Sheet