MT90401AB1 Zarlink, MT90401AB1 Datasheet - Page 13

• Manufacturer Part Number: MT90401AB1
• Description: Framer SDH/SONET 3.3V 80-Pin LQFP EP Tray
• Manufacturer: Zarlink

Specifications of MT90401AB1

• Package: 80LQFP EP
• Number Of Transceivers: 1
• Standard Framing Format: SDH|SONET
• Maximum Supply Current: 150 mA
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V

MT90401
Data Sheet
Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical
to the line frequency), and the input phase offset is small enough such that no phase slope limiting is exhibited, then
the lock signal will be set high.
1.5
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure
5. The Output Interface Circuit uses five Tapped Delay Lines in MT90401 followed by a T1 Divider Circuit, an E1
Divider Circuit, a DS2 Divider Circuit, and a x4/x8 PLL, to generate the required output signals.
Five tapped delay lines are used to generate 8.592 MHz, 11.184 MHz, 16.384 MHz, 12.352 MHz, 12.624 MHz and
19.44 MHz signals.
The E1 Divider Circuit uses the 16.384 MHz signal to generate four clock outputs and three frame pulse outputs.
The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.
These outputs have a nominal 50% duty cycle. The frame pulse outputs (F0o, F8o, and F16o) are generated
directly from the C16 clock.
The T1 Divider Circuit uses the 12.352 MHz signal to generate C1.5o. This output has a nominal 50% duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal
50% duty cycle.
The 19.44 MHz signal is output on the C19o pin and it is multiplied by an internal PLL to generate the 155.52 MHz
clock output on the C155P/N pins. The C155P/N clock has a nominal 50% duty cycle.
The 8.592 MHz and 11.184 MHz signals are multiplied by an internal PLL to generate the 34.368 MHz or
44.736 MHz clock output on the C34/C44 pin. If the internal PLL is dedicated to the C155P/N clock then the
C34/C44 pin will output the 8.592 MHz or 11.184 MHz clocks. The 34.368 Mhz and 44.736 MHz clocks have a
nominal 50% duty cycle. The duty cycles of the 8.592 MHz and 11.184 MHz signals are dependent on the duty
cycle of the 20 MHz clock input to the C20i pin.
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Zarlink Semiconductor Inc.