MT90820AL Zarlink, MT90820AL Datasheet - Page 4

• Manufacturer Part Number: MT90820AL
• Description: Switch Fabric 2K x 2K/1K x 1K/512 x 512 131.072Mbps 5V 100-Pin MQFP Tray
• Manufacturer: Zarlink

Specifications of MT90820AL

• Package: 100MQFP
• Number Of Ports: 16
• Fabric Size: 2K x 2K|1K x 1K|512 x 512
• Switching Bandwidth: 131.072 Mbps
• Switch Core: Non-Blocking
• Port Speed: 2.048|4.096|8.192 Mbps
• Operating Supply Voltage: 5 V

Pin Description
12 - 27
PLCC
30, 54
64, 75
3 - 10
1, 11,
2, 32,
84
63
28
29
31
33
34
35
36
37
38
Pin #
MQFP
31, 41,
56, 66,
76, 99
68-75
81-96
5, 40,
100
100
67
97
98
10
11
6
7
8
9
FE/HCLK
STo8 - 15
STi0 - 15
Name
TRST
CLK
TMS
TDO
TCK
V
TDI
V
F0i
IC
DD
SS
Ground.
+5 Volt Power Supply.
ST-BUS Output 8 to 15 (Three-state Outputs): Serial data Output stream. These
streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value
programmed at bits DR0 - 1 in the IMS register.
ST-BUS Input 0 to 15 (Inputs): Serial data input stream. These streams may have data
rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0 -
1 in the IMS register.
Frame Pulse (Input): When the WFPS pin is low, this input accepts and automatically
identifies frame synchronization signals formatted according to ST-BUS and GCI
specifications. When the WFPS pin is high, this pin accepts a negative frame pulse which
conforms to WFPS formats.
Frame Evaluation / HCLK Clock (Input): When the WFPS pin is low, this pin is the
frame measurement input. When the WFPS pin is high, the HCLK (4.096 MHz clock) is
required for frame alignment in the wide frame pulse (WFP) mode.
Clock (Input): Serial clock for shifting data in/out on the serial streams (STi/o 0 - 15).
Depending upon the value programmed at bits DR0 - 1 in the IMS register, this input
accepts a 4.096, 8.192 or 16.384 MHz clock.
Test Mode Select (Input): JTAG signal that controls the state transitions of the TAP
controller. This pin is pulled high by an internal pull-up when not driven.
Test Serial Data In (Input): JTAG serial test instructions and data are shifted in on this
pin. This pin is pulled high by an internal pull-up when not driven.
Test Serial Data Out (Output): JTAG serial data is output on this pin on the falling edge
of TCK. This pin is held in high impedance state when JTAG scan is not enable.
Test Clock (Input): Provides the clock to the JTAG test logic. This pin is pulled high by
an internal pull-up when not driven.
Test Reset (Input): Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This
pin should be pulsed low on power-up, or held low, to ensure that the MT90820 is in the
normal functional mode.
Internal Connection (Input): Connect to V
low for the MT90820 to function normally and to comply with IEEE 1149 (JTAG)
boundary scan requirements. This pin is pulled low internally when not driven.
Zarlink Semiconductor Inc.
MT90820
4
Description
SS
for normal operation. This pin must be
Data Sheet