CY7B991V-2JCT Cypress Semiconductor Corp, CY7B991V-2JCT Datasheet - Page 5

• Manufacturer Part Number: CY7B991V-2JCT
• Description: Zero Delay Programmable PLL Clock Buffer Single 15MHz to 80MHz 32-Pin PLCC T/R
• Manufacturer: Cypress Semiconductor Corp
• Type: Zero Delay Programmable PLL Clock Bufferr

Specifications of CY7B991V-2JCT

• Package: 32PLCC
• Number Of Elements Per Chip: 1
• Output Frequency Range: 3.75 to 80 MHz
• Operating Temperature: 0 to 70 °C
• Operating Supply Voltage: 3.3 V

Test Mode
The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the CY7B991V to operate
as explained in the
jumper to ground or be tied LOW through a 100-Ω resistor. This enables an external tester to change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected, and input
levels supplied to REF directly controls all outputs. Relative output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs function based only on the connection of their own function select
inputs (xF0 and xF1) and the waveform characteristics of the REF input.
Document Number: 38-07141 Rev. *G
Note
4. FB connected to an output selected for “zero” skew (that is, xF1 = xF0 = MID).
(N/A)
(N/A)
(N/A)
(N/A)
1Fx
2Fx
MM
MH
HM
HH
LM
LH
ML
HL
LL
“Block Diagram Description”
Figure 2. Typical Outputs with FB Connected to a Zero Skew Output Test Mode
LL/HH
(N/A)
(N/A)
(N/A)
(N/A)
3Fx
4Fx
MM
MH
HM
HH
LM
LH
ML
HL
REFInput
FBInput
DIVIDED
INVERT
– 6t
– 4t
– 3t
– 2t
– 1t
+1t
+2t
+3t
+4t
+6t
0t
U
U
U
U
U
U
U
U
U
U
U
on page 4. For testing purposes, any of the three-level inputs can have a removable
[4]
CY7B991V
Page 5 of 17
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