CY7B991V-7JC Cypress Semiconductor Corp, CY7B991V-7JC Datasheet

IC CLK BUFF SKEW 8OUT 32PLCC

CY7B991V-7JC

Manufacturer Part Number
CY7B991V-7JC
Description
IC CLK BUFF SKEW 8OUT 32PLCC
Manufacturer
Cypress Semiconductor Corp
Series
RoboClock™r
Type
Buffer/Driverr
Datasheet

Specifications of CY7B991V-7JC

Number Of Circuits
1
Ratio - Input:output
8:8
Differential - Input:output
Yes/Yes
Input
3-State
Output
LVTTL
Frequency - Max
80MHz
Voltage - Supply
2.97 V ~ 3.63 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-PLCC
Frequency-max
80MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1384

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7B991V-7JC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7B991V-7JC
Manufacturer:
CYPRESS
Quantity:
8 000
Part Number:
CY7B991V-7JC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
CY7B991V-7JCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Cypress Semiconductor Corporation
Document #: 38-07141 Rev. **
Features
Functional Description
The CY7B991V Low Voltage Programmable Skew Clock Buff-
er (LVPSCB) offers user-selectable control over system clock
• All output pair skew <100 ps typical (250 max.)
• 3.75- to 80-MHz output operation
• User-selectable output functions
• Zero input to output delay
• 50% duty-cycle outputs
• LVTTL Outputs drive 50 terminated lines
• Operates from a single 3.3V supply
• Low operating current
• 32-pin PLCC package
• Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Logic Block Diagram
REF
— Selectable skew to 18 ns
— Inverted and non-inverted
— Operation at
— Operation at 2x and 4x input frequency (input as low
FB
TEST
as 3.75 MHz)
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
FS
PHASE
FREQ
DET
SELECT
(THREE
INPUTS
LEVEL)
1
FILTER
2
and
1
4
input frequency
GENERATOR
TIME UNIT
VCO AND
SELECT
MATRIX
SKEW
Low Voltage Programmable Skew Clock Buffer
3901 North First Street
7B991V–1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
functions. These multiple-output clock drivers provide the sys-
tem integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual driv-
ers, arranged as four pairs of user-controllable outputs, can
each drive terminated transmission lines with impedances as
low as 50
and full-swing logic levels (LVTTL).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to 6 time units from their nominal “zero” skew position. The com-
pletely integrated PLL allows external load and transmission line
delay effects to be canceled. When this “zero delay” capability of the
LVPSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to 12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
V
V
GND
GND
4Q1
4Q0
CCQ
3F1
4F0
4F1
CCN
Pin Configuration
San Jose
while delivering minimal and specified output skews
5
6
7
8
9
10
11
12
13
14
4
15
3
16
2
CY7B991V
CA 95134
PLCC
3.3V RoboClock
17
Revised September 24, 2001
1
18 19 20
32 31 30
CY7B991V
29
28
27
26
25
24
23
22
21
408-943-2600
2F0
GND
1F1
1F0
V
1Q0
1Q1
GND
GND
CCN
7B991V–2

Related parts for CY7B991V-7JC

CY7B991V-7JC Summary of contents

Page 1

... Operates from a single 3.3V supply • Low operating current • 32-pin PLCC package • Jitter < 200 ps peak-to-peak (< RMS) Functional Description The CY7B991V Low Voltage Programmable Skew Clock Buff- er (LVPSCB) offers user-selectable control over system clock Logic Block Diagram TEST PHASE ...

Page 2

... HIGH U 22.7 HIGH 38.5 HIGH 62.5 , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination CC / the V NOM CY7B991V 3.3V RoboClock Output Functions 1F0, 2F0, 1Q0, 1Q1, 3F0, 4F0 2Q0, 2Q1 3Q0, 3Q1 LOW –4t Divide by 2 Divide MID – ...

Page 3

... Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output Test Mode The TEST input is a three-level input. In normal system oper- ation, this pin is connected to ground, allowing the CY7B991V to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a removable jumper to ground tied LOW through a 100 resistor ...

Page 4

... CY7B991V should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 8. Total output current per output pair can be approximated by the following expression that includes device current plus load current: CY7B991V [(4 + 0.11F) + [((835 – ...

Page 5

... Jitter Notes: 11. Test measurement levels for the CY7B991V are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. ...

Page 6

... Document #: 38-07141 Rev. ** [2, 11] (continued) Description [ LOW [ MID [ HIGH [13, 14] [13, 15] [13, 17] [13, 17] [13, 17] [13, 17] [12, 18] [19] [20] [20] [12] RMS [12] Peak-to-Peak CY7B991V 3.3V RoboClock CY7B991V–5 Min. Typ. Max. Unit 15 30 MHz 5.0 ns 5.0 ns See Table 1 0.1 0.25 ns 0.25 0.5 ns 0.6 0.7 ns ...

Page 7

... Document #: 38-07141 Rev. ** [2, 11] (continued) Description [ LOW [ MID [ HIGH [13, 14] [13, 15] [13, 17] [13, 17] [13, 17] [13, 17] [12, 18] [19] [20] [20] [12] RMS [12] Peak-to-Peak CY7B991V 3.3V RoboClock CY7B991V–7 Min. Typ. Max. Unit 15 30 MHz 5.0 ns 5.0 ns See Table 1 0.1 0.25 ns 0.3 0.75 ns 0.6 1 ...

Page 8

... AC Timing Diagrams t REF t RPWH REF SKEWPR, t SKEW0,1 OTHER Q INVERTED Q t SKEW3,4 REF DIVIDED SKEW1,3, 4 REF DIVIDED BY 4 Document #: 38-07141 Rev RPWL t ODCV t ODCV t SKEWPR, t SKEW0,1 t SKEW2 t SKEW2 t SKEW3,4 t SKEW3,4 t SKEW2,4 CY7B991V 3.3V RoboClock t JR 7B991V–8 Page ...

Page 9

... Figure 2. Zero-Skew and/or Zero-Delay Clock Driver Figure 2 shows the LVPSCB configured as a zero-skew clock buffer. In this mode the CY7B991V can be used as the basis for a low-skew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and may each drive a terminated transmission line to an inde- pendent load ...

Page 10

... It can multiply by two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. CY7B991V 3.3V RoboClock frequency outputs without concern for ris- REF ...

Page 11

... TEST Figure 8 shows the CY7B991V connected in series to con- struct a zero-skew clock distribution tree between boards. De- lays of the downstream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the mas- Document #: 38-07141 Rev ...

Page 12

... Package Type J65 32-Lead Plastic Leaded Chip Carrier J65 32-Lead Plastic Leaded Chip Carrier J65 32-Lead Plastic Leaded Chip Carrier J65 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier CY7B991V 3.3V RoboClock Operating Range Commercial Commercial Industrial Commercial Page ...

Page 13

... Document Title: CY7B991V 3.3V RoboClock Low Voltage Programmable Skew Clock Buffer Document Number: 38-07141 Issue REV. ECN NO. Date ** 110250 12/17/01 Document #: 38-07141 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00641 to 38-07141 CY7B991V 3.3V RoboClock Page ...

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