CY62157CV33LL-55BAI Cypress Semiconductor Corp, CY62157CV33LL-55BAI Datasheet - Page 6

• Manufacturer Part Number: CY62157CV33LL-55BAI
• Description: SRAM Chip Async Single 3.3V 8M-Bit 512K x 16 55ns 48-Pin FBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62157CV33LL-55BAI

• Package: 48FBGA
• Timing Type: Asynchronous
• Density: 8 Mb
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 19 Bit
• Number Of I/o Lines: 16 Bit
• Number Of Ports: 1
• Number Of Words: 512K

Document #: 38-05014 Rev. *C
Switching Characteristics
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes:
10. t
11. When both byte enables are toggled together this value is 10 ns.
12. The internal Write time of the memory is defined by the overlap of WE, CE
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
8.
9.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
the specified I
At any given temperature and voltage condition, t
any given device.
a Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the
signal that terminates the Write.
HZOE
[11]
Parameter
, t
HZCE
[12]
, t
OL
HZBE
/I
OH
, and t
and 30-pF load capacitance.
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE
CE
CE
CE
BHE/BLE LOW to Data Valid
BHE/BLE LOW to Low-Z
BHE/BLE HIGH to High-Z
Write Cycle Time
CE
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BHE/BLE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
WE HIGH to Low-Z
transitions are measured when the outputs enter a high-impedance state.
1
1
1
1
1
1
HIGH or CE
LOW and CE
LOW and CE
HIGH or CE
LOW and CE
LOW and CE
Over the Operating Range
Description
HZCE
2
2
LOW to Power-down
2
2
2
2
LOW to High-Z
[9]
HIGH to Data Valid
[9, 10]
[9]
[9, 10]
HIGH to Low-Z
HIGH to Power-up
HIGH to Write End
is less than t
[9]
[9, 10]
LZCE
[8]
[9, 10]
, t
[9]
HZBE
1
= V
is less than t
IL
, BHE and/or BLE = V
Min.
55
10
10
55
45
45
45
50
25
5
0
5
0
0
0
5
CC(typ.)
55 ns
LZBE
/2, input pulse levels of 0 to V
, t
HZOE
Max.
55
55
25
20
20
55
55
20
20
IL
is less than t
, CE
2
= V
CY62157CV25/30/33
IH
Min.
. All signals must be ACTIVE to initiate
70
10
10
70
60
60
50
60
30
LZOE
5
0
5
0
0
0
5
, and t
70 ns
CC(typ.)
HZWE
Max.
, and output loading of
70
70
35
25
25
70
70
25
25
is less than t
MoBL™
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Unit
LZWE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
for