CY7C037V-25AC Cypress Semiconductor Corp, CY7C037V-25AC Datasheet - Page 13

• Manufacturer Part Number: CY7C037V-25AC
• Description: SRAM Chip Async Dual 3.3V 576K-Bit 32K x 18 25ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C037V-25AC

• Package: 100TQFP
• Timing Type: Asynchronous
• Density: 576 Kb
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 15 Bit
• Number Of I/o Lines: 18 Bit
• Number Of Ports: 2
• Number Of Words: 32K

Document #: 38-06078 Rev. *A
Switching Waveforms
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
Busy Timing Diagram No. 1 (CE Arbitration)
CE
CE
Right Address Valid First:
Note:
39. If t
L
ADDRESS
ADDRESS
R
Valid First:
ADDRESS
ADDRESS
ADDRESS
ADDRESS
Valid First:
PS
BUSY
BUSY
BUSY
BUSY
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
CE
CE
CE
CE
L,R
L,R
R
R
R
L
R
L
L
L
R
R
L
L
(continued)
t
t
PS
PS
ADDRESS MATCH
ADDRESS MATCH
t
t
RC
RC
or t
or t
t
t
PS
PS
WC
WC
t
t
[39]
BLA
BLA
ADDRESS MATCH
ADDRESS MATCH
[39]
t
t
BLC
BLC
ADDRESS MISMATCH
ADDRESS MISMATCH
t
t
BHA
BHA
t
t
BHC
BHC
CY7C027V/028V
CY7C037V/038V
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